Method and apparatus for providing loop coherency

Claim 2

A data communications network, comprising: a plurality of nodes, each of said plurality of nodes containing at least one device; a primary loop and a secondary loop each being connected to each of said plurality of nodes; a loop coherency circuit associated with each of said plurality of nodes, each of said loop coherency circuits being operably connected to said primary loop and to said secondary loop, said loop coherency circuit for at least partially routing data between the primary loop and the secondary loop upon detecting loss of a steady state signal such that said primary loop and said secondary loop together form a complete loop, wherein said loop coherency circuit comprised first and second loop incoherency detectors being associated with first and second multiplexers, respectively, said first and second loop coherency detectors for detecting a loop incoherency condition and for controlling said first and second multiplexers, respectively to route data between said primary loop and said secondary loop.

Claim 3

A data communications network as claimed in claim 1, wherein said loop coherency circuit includes first and second link redundancy circuits each being connected to said primary loop and to said secondary loop, said first link redundancy circuit being connected to a previous node and said second link redundancy circuit being connected to a succeeding node.

Claim 4

A data communications network as claimed in claim 1, wherein said plurality of nodes contain at least one Fibre-Channel device.

Claim 5

A data communications network as claimed in claim 1, wherein said primary loop is an independent arbitrated loop.

Claim 6

A data communications system as claimed in claim 1, wherein said secondary loop is normally unused for data routing.

Claim 7

A data communications network as claimed in claim 1, wherein said primary loop and said secondary loop together form a complete arbitrated loop during a primary loop incoherency condition.

Claim 8

A data communications network system as claimed in claim 1, wherein said primary loop and said secondary physical loop together form a complete Fibre Channel Arbitrated loop during a primary loop incoherency condition.

Claim 9

A data communications network system as claimed in claim 1, wherein said primary loop and said secondary loop include Fibre-Channel arbitrated loop twin-axis cables.

Claim 10

A data communications network, comprising: a plurality of nodes, each of said plurality of nodes containing at least one device; a primary loop and a secondary loop each being connected to each of said plurality of nodes; a host for allocating storage and I/O resources to each of said plurality of nodes, said host containing at least one device, said primary loop and said secondary loop connecting said host to said plurality of nodes; and a loop coherency circuit associated with each of said plurality of nodes and with said host, each of said loop coherency circuits being operably connected to said primary loop and to said secondary loop, wherein said loop coherency circuit at least partially routes data between the primary loop and the secondary physical loop upon detection of a loop incoherency condition such that said primary loop and said secondary loop together form a complete loop, wherein said loop coherency circuit comprises first and second loop incoherency detectors being associated with first and second multiplexers, respectively, said first and second loop coherency detectors for detecting a loop incoherency condition and for controlling said first and second multiplexers, respectively to route data between said primary loop and said secondary loop.

Claim 11

A data communications network, comprising: a plurality of nodes, each of said plurality of nodes containing at least one device; a primary loop and a secondary loop each being connected to each of said plurality of nodes; a host for allocating storage and I/O resources to each of said plurality of nodes, said host containing at least one device, said primary loop and said secondary loop connecting said host to said plurality of nodes; and a loop coherency circuit associated with each of said plurality of nodes and with said host, each of said loop coherency circuits being operably connected to said primary loop and to said secondary loop, wherein said loop coherency circuit at least partially routes data between the primary loop and the secondary physical loop upon detection of a loop incoherency condition such that said primary loop and said secondary loop together form a complete loop, wherein said loop coherency circuit comprises first and second loop incoherency detectors being associated with first and second multiplexers, respectively, said first and second loop coherency detectors for detecting a loop incoherency condition and for controlling said first and second multiplexers, respectively to route data between said primary loop and said secondary loop.

Claim 12

A data communications network as claimed in claim 9, wherein said loop coherency circuit includes first and second link redundancy circuits each being connected to said primary loop and to said secondary loop, said first link redundancy circuit being connected to a previous node and said second link redundancy circuit being connected to a succeeding node.

Claim 13

A data communications network as claimed in claim 9, wherein said loop coherency circuit associated with said host includes first and second link redundancy circuits each being connected to said primary loop and to said secondary loop, said first link redundancy circuit being connected from said host to a previous node and said second link redundancy circuit being connected from said host to a succeeding node.

Claim 14

A data communications network as claimed in claim 9, wherein said device of said plurality of nodes is a Fibre-Channel device.

Claim 15

A data communications network as claimed in claim 9, wherein said device of said host is a Fibre-Channel device.

Claim 16

A data communications network as claimed in claim 9, wherein said primary loop is an independent arbitrated loop and said secondary physical loop.

Claim 17

A data communications system as claimed in claim 9, wherein said secondary loop is normally unused for data routing.

Claim 18

A data communications network as claimed in claim 9, wherein said primary loop and said secondary physical loop together form a complete arbitrated loop during a primary loop incoherency condition.

Claim 19

A data communications network system as claimed in claim 9, wherein said primary loop and said secondary loop together form a complete Fibre Channel Arbitrated loop during a primary loop incoherency condition.

Claim 20

A data communications network as claimed in claim 9, wherein said primary loop and said secondary loop include Fibre-Channel arbitrated loop twin-axis cables.

Claim 21

A loop coherency circuit for providing loop coherency on a loop data communications system, comprising: first and second multiplexers; and first and second detector circuits, operably connected to said first and second multiplexers, respectively, for controlling the switching of said first and second multiplexers in response to loss of a steady state signal in the loop data communications system.

Claim 22

A loop coherency circuit for providing loop coherency on a loop data communications system, comprising: first and second multiplexers; and first and second detector circuits, operably connected to said first and second multiplexers, respectively, for controlling the switching of said first and second multiplexers in response to loss of a steady state signal in the loop data communications system.

Claim 23

A loop coherency circuit as claimed in claim 19, further comprising an integrated circuit substrate upon which said first and second multiplexers and said first and second detector circuits are fabricated.

Claim 24

A loop coherency circuit for providing loop coherency on a loop data communications system, comprising: first and second multiplexers; and first and second detector circuits, operably connected to said first and second multiplexers, respectively, for controlling the switching of said first and second multiplexers in response to loss of a steady state signal in the loop data communications system, wherein said first detector circuit and first multiplexor are connected by a single path having both data and control information.

Claim 25

A loop coherency circuit for providing loop coherency on a loop data communications system, comprising: first and second multiplexers; and first and second detector circuits, operably connected to said first and second multiplexers, respectively, for controlling the switching of said first and second multiplexers in response to loss of a steady state signal in the loop data communications system, wherein said first detector circuit and first multiplexor are connected by a single path having both data and control information.

Claim 26

The loop coherency circuit of claim 21, wherein the control information is presence of a steady state signal that biases the multiplexer to a first state.

Claim 27

The loop coherency circuit of claim 21, wherein the control information is loss of a steady state signal that biases the multiplexer to a second state.