Display signal interface system between display controller and display apparatus

Claim 2

An interface system for display signals between a display apparatus displayable with high resolution and a display controller for driving the display apparatus, said interface system comprising: a display control gate array for dividing each of display color signals of R (Red), G (Green) and B (Blue) output from the display controller, which are plural-bit digital parallel signals each having a first potential, into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, and dividing a control signal for display into an even-number-th control signal and an odd-number-th control signal and outputting the divided control signals, and frequency-dividing a clock signal with the first potential and a first frequency into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency; a first low voltage parallel-serial conversion circuit for converting each of the even-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the first clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a first clock signal having the second frequency and a second potential lower than the first potential and a control signal of the second potential; a second low voltage parallel-serial conversion circuit for converting each of the odd-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the second clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a second clock signal having the second frequency and a second potential lower than the first potential and a control signal of the second potential; a first low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the second-potential analog serial signals of the even-number-th display color signals output from the first low voltage parallel-serial conversion circuit to a digital parallel signal of the first potential, and boosting and converting the first clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the first low voltage parallel-serial conversion circuit, to a first clock signal of the first potential and the second frequency and a control signal of the first potential; and a second low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the second-potential analog serial signals of the odd-number-th display color signals output from the second low voltage parallel-serial conversion circuit to a digital parallel signal of the first potential, and boosting and converting the second clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the second low voltage parallel-serial conversion circuit, to a second clock signal of the first potential and the second frequency and a control signal of the first potential.

Claim 3

The display signal interface system according to claim 1, wherein said display apparatus displayable with high resolution is a display apparatus displayable with a resolution of no less than 1024 dots×768 lines.

Claim 4

The display signal interface system according to claim 1, wherein said first potential is a CMOS/TTL level, and said second potential is less than 1 volt.

Claim 5

A display signal interface system comprising: a display apparatus displayable with high resolution; a display controller for driving the display apparatus; a display control gate array for dividing each of display color signals of R (Red) G (Green) and B (Blue) output from the display controller, which are plural-bit digital parallel signals each having a first potential, into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, and dividing a control signal for display into an even-number-th control signal and an odd-number-th control signal and outputting the divided control signals, and frequency-dividing a clock signal with the first potential and a first frequency, which is output from the display controller, into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency, a first low voltage parallel-serial conversion circuit for converting each of the even-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the first clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a first clock signal having the second frequency and a second potential lower than the first potential and a control signal of the second potential, and a second low voltage parallel-serial conversion circuit for converting each of the odd-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the second clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a second clock signal having the second frequency and a second potential lower than the first potential and a control signal of the second potential; a first low voltage serial-parallel conversion circuit, provided on a display apparatus side, for converting each of the second-potential analog serial signals of the even-number-th display color signals output from the first low voltage parallel-serial conversion circuit to a digital parallel signal of the first potential, and boosting and converting the first clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the first low voltage parallel-serial conversion circuit, to a first clock signal of the first potential and the second frequency and a control signal of the first potential; and a second low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the second-potential analog serial signals of the odd-number-th display color signals output from the second low voltage parallel-serial conversion circuit to a digital parallel signal of the first potential, and boosting and converting the second clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the second low voltage parallel-serial conversion circuit, to a second clock signal of the first potential and the second frequency and a control signal of the first potential.

Claim 6

A display signal interface system comprising: a display apparatus displayable with high resolution; a display controller for driving the display apparatus; a display control gate array for dividing each of display color signals of R (Red) G (Green) and B (Blue) output from the display controller, which are plural-bit digital parallel signals each having a first potential, into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, and dividing a control signal for display into an even-number-th control signal and an odd-number-th control signal and outputting the divided control signals, and frequency-dividing a clock signal with the first potential and a first frequency, which is output from the display controller, into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency, a first low voltage parallel-serial conversion circuit for converting each of the even-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the first clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a first clock signal having the second frequency and a second potential lower than the first potential and a control signal of the second potential, and a second low voltage parallel-serial conversion circuit for converting each of the odd-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the second clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a second clock signal having the second frequency and a second potential lower than the first potential and a control signal of the second potential; a first low voltage serial-parallel conversion circuit, provided on a display apparatus side, for converting each of the second-potential analog serial signals of the even-number-th display color signals output from the first low voltage parallel-serial conversion circuit to a digital parallel signal of the first potential, and boosting and converting the first clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the first low voltage parallel-serial conversion circuit, to a first clock signal of the first potential and the second frequency and a control signal of the first potential; and a second low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the second-potential analog serial signals of the odd-number-th display color signals output from the second low voltage parallel-serial conversion circuit to a digital parallel signal of the first potential, and boosting and converting the second clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the second low voltage parallel-serial conversion circuit, to a second clock signal of the first potential and the second frequency and a control signal of the first potential.

Claim 7

The display signal interface system according to claim 4, wherein said display apparatus displayable with high resolution is a display apparatus displayable with a resolution of no less than 1024 dots×768 lines.

Claim 8

The display signal interface system according to claim 4, wherein said first potential is a CMOS/TTL level, and said second potential is less than 1 volt.

Claim 9

A computer comprising: a body; a display unit having a flat panel displayable with high resolution; a display controller, provided on the body side, for producing display color signals of R (Red), G (Green) and B (Blue) or digital parallel signals each having a first potential and n-bits (n=a positive integer of 2 or more) per pixel; a display control gate array, provided on the body side, for dividing each of the display color signals output from the display controller into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, and dividing a control signal for display into an even-number-th control signal and an odd-number-th control signal and outputting the divided control signals, and frequency-dividing a clock signal with the first potential and a first frequency, which is output from the display controller, into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency; a first low voltage parallel-serial conversion circuit, provided on the body side, for converting each of the even-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the first clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a first clock signal having the second potential and the second frequency and a control signal of the second potential; a second low voltage parallel-serial conversion circuit, provided on the body side, for converting each of the odd-number-th display color signals output from the display control gate array to an analog serial signal of the second potential, and converting the second clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a second clock signal having the second potential and the second frequency and a control signal of the second potential; a cable for electrically connecting said body and said display unit and serially transferring the display color signals, the clock signal and the control signal which have been converted by said first and second low voltage parallel-serial conversion circuits; a first low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the even-number-th display color signals of the second-potential analog serial signals output from the first low voltage parallel-serial conversion circuit via said cable to a digital parallel signal of the first potential, and converting the first clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the first low voltage parallel-serial conversion circuit, to a first clock signal of the first potential and the second frequency and a control signal of the first potential; and a second low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the odd-number-th display color signals of the second-potential analog serial signals output from the second low voltage parallel-serial conversion circuit via said cable to a digital parallel signal of the first potential, and boosting and converting the second clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the second low voltage parallel-serial conversion circuit, to a second clock signal of the first potential and the second frequency and a control signal of the first potential, the display color signals, the clock signal and the control signal output from the second low voltage serial-parallel conversion circuit being supplied to said flat panel.

Claim 10

A computer comprising: a body; a display unit having a flat panel displayable with high resolution; a display controller, provided on the body side, for producing display color signals of R (Red), G (Green) and B (Blue) or digital parallel signals each having a first potential and n-bits (n=a positive integer of 2 or more) per pixel; a display control gate array, provided on the body side, for dividing each of the display color signals output from the display controller into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, and dividing a control signal for display into an even-number-th control signal and an odd-number-th control signal and outputting the divided control signals, and frequency-dividing a clock signal with the first potential and a first frequency, which is output from the display controller, into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency; a first low voltage parallel-serial conversion circuit, provided on the body side, for converting each of the even-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the first clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a first clock signal having the second potential and the second frequency and a control signal of the second potential; a second low voltage parallel-serial conversion circuit, provided on the body side, for converting each of the odd-number-th display color signals output from the display control gate array to an analog serial signal of the second potential, and converting the second clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a second clock signal having the second potential and the second frequency and a control signal of the second potential; a cable for electrically connecting said body and said display unit and serially transferring the display color signals, the clock signal and the control signal which have been converted by said first and second low voltage parallel-serial conversion circuits; a first low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the even-number-th display color signals of the second-potential analog serial signals output from the first low voltage parallel-serial conversion circuit via said cable to a digital parallel signal of the first potential, and converting the first clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the first low voltage parallel-serial conversion circuit, to a first clock signal of the first potential and the second frequency and a control signal of the first potential; and a second low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the odd-number-th display color signals of the second-potential analog serial signals output from the second low voltage parallel-serial conversion circuit via said cable to a digital parallel signal of the first potential, and boosting and converting the second clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the second low voltage parallel-serial conversion circuit, to a second clock signal of the first potential and the second frequency and a control signal of the first potential, the display color signals, the clock signal and the control signal output from the second low voltage serial-parallel conversion circuit being supplied to said flat panel.

Claim 11

The computer according to claim 7, wherein said display apparatus displayable with high resolution is a display apparatus displayable with a resolution of no less than 1024 dots×768 lines.

Claim 12

The computer according to claim 7, wherein said first potential is a CMOS/TTL level, and said second potential is less than 1 volt.

Claim 13

A computer comprising: a body; a display unit having a flat panel displayable with high resolution; a display controller, provided on the body side, for producing display color signals of R (Red), G (Green) and B (Blue) or digital parallel signals each having a first potential and n-bits (n=a positive integer of 2 or more) per pixel, said display controller including a display control gate array for dividing each of the display color signals into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, and dividing a control signal for display into an even-number-th control signal and an odd-number-th control signal and outputting the divided control signals, and frequency-dividing a clock signal with the first potential and a first frequency into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency, a first low voltage parallel-serial conversion circuit, provided on the body side, for converting each of the even-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the first clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a first clock signal having the second potential and the second frequency and a control signal of the second potential, and a second low voltage parallel-serial conversion circuit, provided on the body side, for converting each of the odd-number-th display color signals output from the display control gate array to an analog serial signal of the second potential, and converting the second clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a second clock signal having the second potential and the second frequency and a control signal of the second potential; a cable for electrically connecting said body and said display unit and serially transferring the display color signals, the clock signal and the control signal which have been converted by said second low voltage parallel-serial conversion circuit; a first low voltage serial-parallel conversion circuit, provided in the display unit, for converting each of the even-number-th display color signals of the second-potential analog serial signals output from the first low voltage parallel-serial conversion circuit via said cable to a digital parallel signal of the first potential, and converting the first clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the first low voltage parallel-serial conversion circuit, to a first clock signal of the first potential and the second frequency and a control signal of the first potential; and a second low voltage serial-parallel conversion circuit, provided in the display unit, for converting each of the odd-number-th display color signals of the second-potential analog serial signals output from the second low voltage parallel-serial conversion circuit via said cable to a digital parallel signal of the first potential, and boosting and converting the second clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the second low voltage parallel-serial conversion circuit, to a second clock signal of the first potential and the second frequency and a control signal of the first potential, the display color signals, the clock signal and the control signal output from the second low voltage serial-parallel conversion circuit being supplied to said flat panel.

Claim 14

A computer comprising: a body; a display unit having a flat panel displayable with high resolution; a display controller, provided on the body side, for producing display color signals of R (Red), G (Green) and B (Blue) or digital parallel signals each having a first potential and n-bits (n=a positive integer of 2 or more) per pixel, said display controller including a display control gate array for dividing each of the display color signals into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, and dividing a control signal for display into an even-number-th control signal and an odd-number-th control signal and outputting the divided control signals, and frequency-dividing a clock signal with the first potential and a first frequency into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency, a first low voltage parallel-serial conversion circuit, provided on the body side, for converting each of the even-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the first clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a first clock signal having the second potential and the second frequency and a control signal of the second potential, and a second low voltage parallel-serial conversion circuit, provided on the body side, for converting each of the odd-number-th display color signals output from the display control gate array to an analog serial signal of the second potential, and converting the second clock signal of the first potential and the second frequency and the control signal of the first potential, which are output from the display control gate array, to a second clock signal having the second potential and the second frequency and a control signal of the second potential; a cable for electrically connecting said body and said display unit and serially transferring the display color signals, the clock signal and the control signal which have been converted by said second low voltage parallel-serial conversion circuit; a first low voltage serial-parallel conversion circuit, provided in the display unit, for converting each of the even-number-th display color signals of the second-potential analog serial signals output from the first low voltage parallel-serial conversion circuit via said cable to a digital parallel signal of the first potential, and converting the first clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the first low voltage parallel-serial conversion circuit, to a first clock signal of the first potential and the second frequency and a control signal of the first potential; and a second low voltage serial-parallel conversion circuit, provided in the display unit, for converting each of the odd-number-th display color signals of the second-potential analog serial signals output from the second low voltage parallel-serial conversion circuit via said cable to a digital parallel signal of the first potential, and boosting and converting the second clock signal of the second potential and the second frequency and the control signal of the second potential, which are output from the second low voltage parallel-serial conversion circuit, to a second clock signal of the first potential and the second frequency and a control signal of the first potential, the display color signals, the clock signal and the control signal output from the second low voltage serial-parallel conversion circuit being supplied to said flat panel.

Claim 15

The computer according to claim 10, wherein said display apparatus displayable with high resolution is a display apparatus displayable with a resolution of no less than 1024 dots×768 lines.

Claim 16

The computer according to claim 10, wherein said first potential is a CMOS/TTL level, and said second potential is less than 1 volt.

Claim 17

A display signal interface system in a computer comprising a body, a display unit with a flat panel, a cable for electrically connecting the body and the display unit, and a display controller for producing digital parallel display color signals each having a first potential and n-bits (n=an integer of 2 or more) per pixel, a display clock signal of the first potential and a control signal of the first potential, said display signal interface system comprising: means for dividing each of the produced display color signals into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, for dividing the control signal into an even-number-th control signal and an odd-number-th control signal and outputting the divided control signals, and for frequency-dividing the clock signal with the first potential and a first frequency into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency; means for converting each of the even-number-th display color signals and the control signal to an analog serial signal of a second potential lower than said first potential, for converting the first clock signal of the first potential and the second frequency to a first clock signal having the second potential and the second frequency, for converting simultaneously each of the odd-number-th display color signals and the control signal to an analog serial signal of the second potential, for converting the second clock signal of the first potential and the second frequency to a second clock signal having the second potential and the second frequency, and for outputting all the converted signals to the cable; and means for converting each of the even-number-th display color signals of the second-potential analog serial signals supplied via the cable to a digital parallel signal of the first potential on a display unit side, for converting the even-number-th control signal to a digital signal of the first potential, for boosting and converting the first clock signal of the second potential and the second frequency to a first clock signal of the first potential and the second frequency, and simultaneously for converting each of the odd-number-th display color signals of the second-potential analog serial signals supplied via the cable to a digital parallel signal of the first potential, for converting the odd-number-th control signal to a digital signal of the first potential, and for boosting and converting the second clock signal of the second potential and the second frequency to a second clock signal of the first potential and the second frequency, thereby driving the flat panel.

Claim 18

A display signal interface system in a computer comprising a body, a display unit with a flat panel, a cable for electrically connecting the body and the display unit, and a display controller for producing digital parallel display color signals each having a first potential and n-bits (n=an integer of 2 or more) per pixel, a display clock signal of the first potential and a control signal of the first potential, said display signal interface system comprising: means for dividing each of the produced display color signals into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, for dividing the control signal into an even-number-th control signal and an odd-number-th control signal and outputting the divided control signals, and for frequency-dividing the clock signal with the first potential and a first frequency into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency; means for converting each of the even-number-th display color signals and the control signal to an analog serial signal of a second potential lower than said first potential, for converting the first clock signal of the first potential and the second frequency to a first clock signal having the second potential and the second frequency, for converting simultaneously each of the odd-number-th display color signals and the control signal to an analog serial signal of the second potential, for converting the second clock signal of the first potential and the second frequency to a second clock signal having the second potential and the second frequency, and for outputting all the converted signals to the cable; and means for converting each of the even-number-th display color signals of the second-potential analog serial signals supplied via the cable to a digital parallel signal of the first potential on a display unit side, for converting the even-number-th control signal to a digital signal of the first potential, for boosting and converting the first clock signal of the second potential and the second frequency to a first clock signal of the first potential and the second frequency, and simultaneously for converting each of the odd-number-th display color signals of the second-potential analog serial signals supplied via the cable to a digital parallel signal of the first potential, for converting the odd-number-th control signal to a digital signal of the first potential, and for boosting and converting the second clock signal of the second potential and the second frequency to a second clock signal of the first potential and the second frequency, thereby driving the flat panel.

Claim 19

The display signal interface system according to claim 13, wherein said flat panel is displayable with a resolution of no less than 1024 dots×768 lines.

Claim 20

The display signal interface system according to claim 13, wherein said first potential is a CMOS/TTL level, and said second potential is less than 1 volt.

Claim 21

An interface system for display signals between a display apparatus displayable with high resolution and a display controller for driving the display apparatus, said interface system comprising: a display control gate array for dividing each of display color signals of R (Red), G (Green) and B (Blue), which are output from the display controller and are plural-bit digital parallel signals each having a first potential, a signal representing the beginning of effective display data, field pulses each having the first potential and corresponding to one screen cycle, and a latch pulse corresponding to one line cycle, into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, and frequency-dividing a clock signal with the first potential and a first frequency into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency; a first low voltage parallel-serial conversion circuit for converting each of the even-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the first clock signal of the first potential and the second frequency, which is output from the display control gate array, to a first clock signal having the second frequency and a second potential lower than the first potential; a second low voltage parallel-serial conversion circuit for converting each of the odd-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the second clock signal of the first potential and the second frequency, which is output from the display control gate array, to a second clock signal having the second frequency and a second potential lower than the first potential; a first low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the even-number-th display color signals of the second-potential analog serial signals output from the first low voltage parallel-serial conversion circuit to a digital parallel signal of the first potential, and boosting and converting the first clock signal of the second potential and the second frequency, which is output from the first low voltage parallel-serial conversion circuit, to a first clock signal of the first potential and the second frequency; and a second low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the odd-number-th display color signals of the second-potential analog serial signals output from the second low voltage parallel-serial conversion circuit to a digital parallel signal of the first potential, and boosting and converting the second clock signal of the second potential and the second frequency, which is output from the second low voltage parallel-serial conversion circuit, to a second clock signal of the first potential and the second frequency.

Claim 22

An interface system for display signals between a display apparatus displayable with high resolution and a display controller for driving the display apparatus, said interface system comprising: a display control gate array for dividing each of display color signals of R (Red), G (Green) and B (Blue), which are output from the display controller and are plural-bit digital parallel signals each having a first potential, a signal representing the beginning of effective display data, field pulses each having the first potential and corresponding to one screen cycle, and a latch pulse corresponding to one line cycle, into an even-number-th display color signal and an odd-number-th display color signal and outputting the divided display color signals, and frequency-dividing a clock signal with the first potential and a first frequency into a first clock signal and a second clock signal each having the first potential and a second frequency lower than the first frequency; a first low voltage parallel-serial conversion circuit for converting each of the even-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the first clock signal of the first potential and the second frequency, which is output from the display control gate array, to a first clock signal having the second frequency and a second potential lower than the first potential; a second low voltage parallel-serial conversion circuit for converting each of the odd-number-th display color signals output from the display control gate array to an analog serial signal of a second potential lower than said first potential, and converting the second clock signal of the first potential and the second frequency, which is output from the display control gate array, to a second clock signal having the second frequency and a second potential lower than the first potential; a first low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the even-number-th display color signals of the second-potential analog serial signals output from the first low voltage parallel-serial conversion circuit to a digital parallel signal of the first potential, and boosting and converting the first clock signal of the second potential and the second frequency, which is output from the first low voltage parallel-serial conversion circuit, to a first clock signal of the first potential and the second frequency; and a second low voltage serial-parallel conversion circuit, provided on the display apparatus side, for converting each of the odd-number-th display color signals of the second-potential analog serial signals output from the second low voltage parallel-serial conversion circuit to a digital parallel signal of the first potential, and boosting and converting the second clock signal of the second potential and the second frequency, which is output from the second low voltage parallel-serial conversion circuit, to a second clock signal of the first potential and the second frequency.