US5982459A
Expired / Lapsed
US
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Integrated multimedia communications processor and codec
Assignee: 8X8 Inc
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Filing: 1997-06-11
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Granted: 1999-11-09
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Expires: 2017-06-11
Abstract
Abstract A multimedia processor contains a general purpose RISC and video processors which operate in parallel to execute software for combined video and audio bit stream coding and decoding. The RISC processor controls operation of the multimedia processor and performs bit stream parsing and coding, audio compression and decompression, and general processing for embedded applications. The video processor performs video encoding and decoding functions such as scaling, filtering, decimation, and DCT transforms. The RISC processor and the video processor each have separate data buses which are interconnected through a portal circuit and a Huffman codec. Each data bus has a DMA controller which transfers data to and from a memory interface to an external memory. DMA channels serve I/O interface resources coupled to the data buses and can form buffers in the external memory. This reduces the need for on-chip FIFO buffers and separate buffers between the multimedia processor and attached devices.
Inventors
- 👤 Jan Fandrianto
- 👤 Bryan R. Martin
- 👤 Doug G. Neubauer
- 👤 Duat H. Tran
- 👤 Matthew D. Cressa
- 👤 Arijanto Soemedi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:26
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/14; H04N7/141; H04N7/142
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
128 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, the data signal including at least a serial bit stream of non-byte aligned audio data and video data, the video communications processing arrangement comprising: a communications interface configured to receive the data signal; a programmable supervisory processor, the supervisory processor generating a configuration control signal in response to communication channel parameters; a reconfigurable parsing circuit coupled to receive the data signal from the communications interface, the parsing circuit being configured, in response to the configuration control signal, to separate the video data and the audio data in the data signal in accordance with the communication channel parameters; and a programmable video processor configured and arranged to process the separated video data.
Claim 2
Dependent Claim
128 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, the data signal including at least a serial bit stream of non-byte aligned audio data and video data, the video communications processing arrangement comprising: a communications interface configured to receive the data signal; a programmable supervisory processor, the supervisory processor generating a configuration control signal in response to communication channel parameters; a reconfigurable parsing circuit coupled to receive the data signal from the communications interface, the parsing circuit being configured, in response to the configuration control signal, to separate the video data and the audio data in the data signal in accordance with the communication channel parameters; and a programmable video processor configured and arranged to process the separated video data.
Claim 3
Dependent Claim
25 words
The video communications processing arrangement of claim 1, wherein the data signal is time division multiplexed (TDM) and the communications interface comprising a TDM interface.
Claim 4
Dependent Claim
24 words
The video communications processing arrangement of claim 1, wherein the programmable video processor is further configured and arranged to process the separated audio data.
Claim 5
Dependent Claim
25 words
The video communications processing arrangement of claim 1, wherein the supervisory processor, the video processor and the parsing circuit are formed within a single chip.
Claim 6
Dependent Claim
27 words
The video communications processing arrangement of claim 1, wherein the communication channel parameters comprise a communication protocol used to transmit the data stream on the communications channel.
Claim 7
Dependent Claim
34 words
The video communications processing arrangement of claim 4, further comprising a memory, accessible by the supervisor processor, the video processor and the parsing circuit, for temporarily storing the separated video data and audio data.
Claim 8
Dependent Claim
17 words
The video communications processing arrangement of claim 6, wherein the memory is external to the single chip.
Claim 9
Dependent Claim
54 words
The video communications processing arrangement of claim 7, further comprising a direct memory access (DMA) controller formed on the chip with the supervisory processor, the video processor, and the parsing circuit, to control access to the memory, the memory functioning as FIFO buffers for the supervisory processor, the video processor, and the parsing circuit.
Claim 10
Dependent Claim
37 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, according to claim 1, wherein the programmable supervisory processor is programmable independently from the programmability of the programmable video processor.
Claim 11
Dependent Claim
36 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, according to claim 1, the programmable video processor is programmable independently from the programmability of the programmable supervisory processor.
Claim 12
Dependent Claim
70 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, according to claim 1, wherein the supervisor processor, the video processor and the parsing circuit are implemented on a single chip, and further comprising an external SRAM circuit, and a RISC-DMA circuit formed with the supervisory processor, the video processor, and the parsing circuit, to manage data communication with the external SRAM circuit.
Claim 13
Dependent Claim
41 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, according to claim 11, wherein the single chip further includes an audio port, a TDM port, a host port, a Huffman data processing circuit.
Claim 14
Dependent Claim
49 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, according to claim 12, wherein the RISC-DMA circuit manages data flow between the external SRAM circuit and the audio port, the TDM port, the host port, and the Huffman data processing circuit.
Claim 15
Dependent Claim
50 words
A video communications processing method for processing a data signal received in a video communications processing arrangement, according to claim 1, wherein the supervisor processor, the video processor and the parsing circuit are implemented on a single chip along with a boot ROM storing a monitor application for self-booting operation.
Claim 16
Dependent Claim
60 words
A video communications processing method for processing a data signal received in a video communications processing arrangement, according to claim 1, further comprising a RISC circuit formed with the supervisory processor and the video processor, and further including a bit-manipulating non-programmable circuit, responsive to data passed from the RISC circuit, adapted to find frame alignment and to perform data validation.
Claim 17
Dependent Claim
121 words
A video communications processing method for processing a data signal received in a video communications processing arrangement including a supervisory processor and a video processor from one or more communication channels, the data signal including at least a serial bit stream of non-byte aligned audio data and video data, the video communications processing method comprising: providing the data signal received from the communication channels to the supervisory processor; identifying, using the supervisory processor, communication channel parameters for the data signal; parsing the data signal to separate the video data and the audio data in the data signal based on the identified communication channel parameters; and storing the separated video data in a memory accessible by the video processor for processing thereby.
Claim 18
Dependent Claim
121 words
A video communications processing method for processing a data signal received in a video communications processing arrangement including a supervisory processor and a video processor from one or more communication channels, the data signal including at least a serial bit stream of non-byte aligned audio data and video data, the video communications processing method comprising: providing the data signal received from the communication channels to the supervisory processor; identifying, using the supervisory processor, communication channel parameters for the data signal; parsing the data signal to separate the video data and the audio data in the data signal based on the identified communication channel parameters; and storing the separated video data in a memory accessible by the video processor for processing thereby.
Claim 19
Dependent Claim
118 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, the data signal including at least a serial bit stream of non-byte aligned audio data and video data, comprising: means for interfacing with the communication channel to receive the data signal; supervisory processing means for identifying communication channel parameters for the data signal and for generating a configuration control signal indicative of the communication channel parameters; means, configured in response to the configuration control signal, for parsing the data signal to separate the video data from the audio data; a memory for storing the separated video data; and video processing means, coupled to the memory, for processing the separated video data.
Claim 20
Dependent Claim
118 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, the data signal including at least a serial bit stream of non-byte aligned audio data and video data, comprising: means for interfacing with the communication channel to receive the data signal; supervisory processing means for identifying communication channel parameters for the data signal and for generating a configuration control signal indicative of the communication channel parameters; means, configured in response to the configuration control signal, for parsing the data signal to separate the video data from the audio data; a memory for storing the separated video data; and video processing means, coupled to the memory, for processing the separated video data.
Claim 21
Dependent Claim
45 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, according to claim 17, wherein at least one of the supervisory processing means and the video processing means is independently programmable relative to any programmability of the other.
Claim 22
Dependent Claim
80 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, according to claim 17, wherein each of the supervisor processor and the video processor is programmable, and wherein the supervisor processor, the video processor and the parsing circuit are implemented on a single chip, along with a serial audio port, a serial communication port, a programmable audio processor, a programmable video-in interface, a programmable video-out interface, and an embedded ROM for self-booting operation.
Claim 23
Dependent Claim
84 words
A video communications processing arrangement for processing a data signal received from one or more communication channels, according to claim 17, wherein the supervisor processor, the video processor and the parsing circuit are implemented with a RISC-DMA circuit on a single chip, along with separately accessible internal SRAM and DRAM busses, wherein the RISC-DMA circuit manages transfer of data between an SRAM circuit and a DRAM circuit, the SRAM circuit and the DRAM circuit are respectively connected to the internal SRAM and DRAM busses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |