US5982040A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method for manufacturing the same
Assignee: Toshiba Corp
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Filing: 1997-11-14
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Granted: 1999-11-09
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Expires: 2017-11-14
Abstract
Abstract A semiconductor device includes a semiconductor substrate having a main surface, and a multi-layered wiring layer formed on the main surface of the semiconductor substrate, the multi-layered wiring layer having a plurality of wiring layers insulatively laminated, wherein the melting points of the plurality of wiring layers are set gradually lower in a direction towards the higher-level side.
Inventors
- 👤 Masaki Yamada
- 👤 Minakshisundaran Balasubramanian Anand
- 👤 Hideki Shibata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:04
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/40; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4405
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
103 words
A semiconductor device comprising: a semiconductor substrate having a main surface; and a multi-layered wiring layer formed on said main surface of said semiconductor substrate, said multi-layered wiring layer including a plurality of wiring layers insulatively laminated; wherein each of said wiring layers constructing said multi-layered wiring layer is formed of the same base metal, and a melting point of each of said plurality of wiring layers is set lower than that of one of said wiring layers which lies at a lower level by introducing at least one doping element into said base metal in at least one of said wiring layers.
Claim 2
Dependent Claim
103 words
A semiconductor device comprising: a semiconductor substrate having a main surface; and a multi-layered wiring layer formed on said main surface of said semiconductor substrate, said multi-layered wiring layer including a plurality of wiring layers insulatively laminated; wherein each of said wiring layers constructing said multi-layered wiring layer is formed of the same base metal, and a melting point of each of said plurality of wiring layers is set lower than that of one of said wiring layers which lies at a lower level by introducing at least one doping element into said base metal in at least one of said wiring layers.
Claim 3
Dependent Claim
34 words
A semiconductor device according to claim 1, wherein said at least one doping element includes different types of doping elements introduced into said base metal in at least two layers among said wiring layers.
Claim 4
Dependent Claim
35 words
A semiconductor device according to claim 1, wherein said at least one doping element includes a doping element introduced at different concentrations into said base metal in at least two layers among said wiring layers.
Claim 5
Dependent Claim
41 words
A semiconductor device according to claim 1, wherein each of said plurality of wiring layers is formed in a corresponding one of concave portions formed in a plurality of insulating films laminated on an upper surface side of said semiconductor substrate.
Claim 6
Dependent Claim
13 words
A semiconductor device according to claim 1, wherein said base metal is aluminum.
References Cited (Backward Citations)
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JPS6038837A
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JPS6257234A
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JPH0427151A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |