Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
229 words
A method for making a semiconductor interconnect structure having a semiconductor substrate that includes a first low K dielectric material that overlies the semiconductor substrate, the first low K dielectric material supports a patterned first level of metallization, and a second low K dielectric material overlies the first low K dielectric material and the patterned first level of metallization, comprising: forming at least one via hole through the second low K dielectric material down to the patterned first level of metallization; depositing a seed layer over the second low K dielectric material and in the at least one via hole; depositing an aluminum layer over the seed layer that overlies the second low K dielectric material and the at least one via hole such that the at least one via hole is an aluminum filled via hole; removing the aluminum layer and the seed layer overlying the second low K dielectric material using a chemical mechanical polishing operation that is configured to remove a top portion of the aluminum filled via hole, the removed portion defining a recessed gap of between about 500 angstroms and about 2,500 angstroms at the top portion of the aluminum filled via hole; and depositing an electromigration barrier cap within the recessed gap of the aluminum filled via hole to prevent aluminum atoms from electromigrating out of the aluminum filled via hole during operation.
Claim 2
Independent Claim
229 words
A method for making a semiconductor interconnect structure having a semiconductor substrate that includes a first low K dielectric material that overlies the semiconductor substrate, the first low K dielectric material supports a patterned first level of metallization, and a second low K dielectric material overlies the first low K dielectric material and the patterned first level of metallization, comprising: forming at least one via hole through the second low K dielectric material down to the patterned first level of metallization; depositing a seed layer over the second low K dielectric material and in the at least one via hole; depositing an aluminum layer over the seed layer that overlies the second low K dielectric material and the at least one via hole such that the at least one via hole is an aluminum filled via hole; removing the aluminum layer and the seed layer overlying the second low K dielectric material using a chemical mechanical polishing operation that is configured to remove a top portion of the aluminum filled via hole, the removed portion defining a recessed gap of between about 500 angstroms and about 2,500 angstroms at the top portion of the aluminum filled via hole; and depositing an electromigration barrier cap within the recessed gap of the aluminum filled via hole to prevent aluminum atoms from electromigrating out of the aluminum filled via hole during operation.
Claim 3
Dependent Claim
62 words
A method for making a semiconductor interconnect structure as recited in claim 1, further comprising: depositing an interconnect metallization layer over the second low K dielectric material and the electromigration barrier cap; and pattering the interconnect metallization layer such that a line of the patterned interconnect metallization layer is in contact with the electromigration barrier cap of the aluminum filled via hole.
Claim 4
Dependent Claim
42 words
A method for making a semiconductor interconnect structure as recited in claim 2, wherein the patterning of the interconnect metallization layer is performed through a plasma etch that does not etch through the electromigration barrier cap of the aluminum filled via hole.
Claim 5
Dependent Claim
38 words
A method for making a semiconductor interconnect structure as recited in claim 3, wherein the electromigration barrier cap is a material selected from the group consisting of titanium tungsten (TiW), tungsten (W), and tungsten silicide (WSi 2 ).
Claim 6
Dependent Claim
44 words
A method for making a semiconductor interconnect structure as recited in claim 3, wherein the plasma etch implements a Cl 2 /BCL 3 chemistry having a Cl 2 flow rate of about 60 sccms, and a BCL 3 flow rate of about 30 sccms.
Claim 7
Dependent Claim
38 words
A method for making a semiconductor interconnect structure as recited in claim 1, wherein the first low K dielectric material and the second low K dielectric material is have a K value of between about 2 and 4.
Claim 8
Dependent Claim
72 words
A method for making a semiconductor interconnect structure as recited in claim 1, wherein the removing the aluminum layer and the seed layer is performed using a chemical mechanical polishing operation having a slurry chemical including alumina particles, deionized water and an oxidant (H 2 O 2 ), the slurry chemical being configured to assist in the formation of the recessed gap at the top portion of the aluminum filled via hole.