Apparatus, systems and methods for controlling data overlay in multimedia data processing and display systems using mask techniques

Claim 2

An overlay control system comprising: a frame buffer for storing words of graphic data, words of video data and an overlay control mask; mask generation circuitry for generating said overlay control mask for storage in said frame buffer from a mask object, said mask object having fewer bits than said overlay control mask; and mask controlled overlay selection circuitry operable in response to bits of said overlay control mask retrieved from said frame buffer to selectively retrieve and output words of said video data stored in said frame buffer.

Claim 3

The overlay control system of claim 1, wherein the mask generation circuitry further comprises: circuitry for generating a plurality addresses to storage locations within said frame buffer, said locations for storing bits defining a selected region of said overlay control mask; circuitry for generating mask data words of a selected logic value; and circuitry for selectively presenting said addresses and said mask data words to said frame buffer such that said mask data words are written to said storage locations thereby defining said region of said overlay control mask.

Claim 4

The overlay control system of claim 2, wherein said circuitry for generating a plurality of addresses comprises: an x-position counter for counting, in response to a clock, from an initial x-position value to a final x-position value; a y-position counter for counting from an initial y-position value to a final y-position value when a count in said x-position counter reaches said final x-position value, said x-position counter resetting to said initial x-position value and continuing to count when a current count in said y-position counter has not reached said final y-position value; an x-position register for storing a first portion of an address, to a first location in said frame buffer for storing a first bit of said region; a y-position counter for storing a second portion of said address; circuitry for modifying said first portion being stored in said x-position register with each change in count of said x-position counter; and circuitry for modifying said second portion being stored in said y-position counter when said count in said x-position counter reaches said final value.

Claim 5

The overlay control system of claim 2, further comprising a data formatter having a plurality of storage locations each pointed to by selected bits of an address, said formatter accumulating for output as a data word a selected number of bits of said selected logic value in response to said selected bits of corresponding ones of said addresses.

Claim 6

The overlay control system of claim 1, wherein said mask controlled overlay selection circuitry comprises: display-position control circuitry for determining when a position of a raster scan generating a display screen has reached a video window within said display screen; circuitry for generating an address to said frame buffer to retrieve corresponding bits of said overlay control mask when said raster scan has reached said video window; a register for storing said bits of said overlay control mask retrieved from said frame buffer; circuitry for generating addresses to said frame buffer to retrieve words of said video data corresponding to said video window; and an overlay selector for selectively outputting said words of said video data retrieved from said frame buffer in response to said bits of said overlay control mask stored in the register.

Claim 7

The overlay control system of claim 5 and further comprising comparison circuitry for comparing selected ones of said bits stored in said register to bits from display-position control circuitry and generating, in response, a video read request signal to control circuitry associated with said frame buffer, said control circuitry providing in response to said video read request signal, a video read grant signal to circuitry for generating addresses to enable the retrieval of said corresponding bits of said mask.

Claim 8

A display system comprising: a display device for generating a display on a display screen; a frame buffer having a graphics memory area and a mask memory area; graphics data processing circuitry for processing a graphics data stream, said graphics data processing circuitry controlling transfer of graphics data to and from the graphics memory area of said frame buffer; mask generation circuitry for generating a mask for storage in the mask memory area of said frame buffer from a mask object, said mask object having fewer bits than said mask; video data processing circuitry for processing a video data stream including mask controlled circuitry operable in response to bits of said mask retrieved from said frame buffer to selectively retrieve words of said video data stream stored in said frame buffer; and mask controlled output selection circuitry for selecting for output to said display device in response to said bits of said mask between words of graphics data retrieved from said frame buffer by said graphics processing circuitry and words of said video data retrieved from said frame buffer by said video data processing circuitry.

Claim 9

A display system comprising: a display device for generating a display on a display screen; a frame buffer having a graphics memory area and a mask memory area; graphics data processing circuitry for processing a graphics data stream, said graphics data processing circuitry controlling transfer of graphics data to and from the graphics memory area of said frame buffer; mask generation circuitry for generating a mask for storage in the mask memory area of said frame buffer from a mask object, said mask object having fewer bits than said mask; video data processing circuitry for processing a video data stream including mask controlled circuitry operable in response to bits of said mask retrieved from said frame buffer to selectively retrieve words of said video data stream stored in said frame buffer; and mask controlled output selection circuitry for selecting for output to said display device in response to said bits of said mask between words of graphics data retrieved from said frame buffer by said graphics processing circuitry and words of said video data retrieved from said frame buffer by said video data processing circuitry.

Claim 10

The system of claim 7, wherein the mask generation circuitry further comprises: circuitry for generating a plurality of addresses to storage locations within a mask object storing bits, defining a selected region of a mask; circuitry for generating mask data words of a selected logic value; and circuitry for selectively presenting said addresses and said data words to said frame buffer such that said mask data words are written to said storage locations in said mask object to define said selected region of said mask.

Claim 11

The display system of claim 8, wherein said circuitry for generating a plurality of addresses comprises: an x-position counter for counting in response to a clock from an initial x-position value to a final x-position value; a y-position counter for counting from a initial y-position value to a final y-position value when a count in said x-position counter reaches said final x-position value, said x-position counter resetting to said initial x-position value and continuing to count when a current count in said y-position counter has not reached said final y-position value; an x-position register for storing a first portion of an address to a first location in said frame buffer for storing a first bit of said region; a y-position counter for storing a second portion of said address; circuitry for modifying said first portion being stored in said x-position register with each change in count of said x-position counter; and circuitry for modifying said second portion being stored in said y-position counter when said count in said x-position counter reaches said final value.

Claim 12

The display system of claim 8, wherein said circuitry for generating mask data words comprises a data formatter having a plurality of storage locations each pointed to by selected bits of an address, said data formatter accumulating for output as a mask data word a selected number of bits of said selected logic value in response to at least some bits of corresponding ones of said addresses.

Claim 13

The display system of claim 10, wherein said data formatter accumulates 64-bit mask data words for storage in said mask object.

Claim 14

The display system of claim 7, wherein said mask controlled circuitry of said video processing comprises: display position control circuitry for determining when a position of a raster scan generating a said display screen on said display device has reached a video window within said display screen; circuitry for generating an address to said frame buffer to retrieve bits of said mask from said mask object when said raster scan has reached said video window; a register for storing said bits of said mask retrieved from said frame buffer; circuitry for generating addresses to said frame buffer to retrieve words of said video data corresponding to said video window; and comparison circuitry for comparing selected ones of said bits retrieved from said register to bits from display-position control circuitry and generating in response a video read request to control circuitry associated with said frame buffer, said control circuitry providing in response to said read request a video read grant to circuitry for generating addresses to enable the retrieval of said video data corresponding to said video window.

Claim 15

The display system of claim 12, wherein said mask controlled output selection circuitry received said bits of said mack from said register an performs an output selection in response thereto.

Claim 16

The display system of claim 12, wherein said register stores mask bits as 64-bit blocks received from said mask object.

Claim 17

The display system of claim 12, wherein said comparison circuitry compares 4 said selected bits at a time.