US5974438A
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US
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Scoreboard for cached multi-thread processes
Assignee: Hewlett Packard Enterprise Development LP
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Filing: 1996-12-31
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Granted: 1999-10-26
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Expires: 2016-12-31
Abstract
Abstract A computer system comprising at least one processor and associated cache memory, and a plurality of registers to keep track of the number of cache memory lines associated with each process thread running in the computer system. Each process thread is assigned to one of the plurality of registers of each level of cache that is being monitored. The number of cache memory lines associated with each process thread in a particular level of the cache is stored as a number value in the assigned register and will increment as more cache memory lines are used for the process thread and will decrement as less cache memory lines are used. The number value in the register is defined as the "process thread temperature." Larger number values indicate warmer process thread temperature and smaller number values indicate cooler process thread temperature. Process thread temperatures are relative and indicate the cache memory line usage by the process threads running in the computer system at a particular level of cache. By keeping track or "score" of the number values (temperatures) in each of these registers called "scoreboard registers," the scheduler algorithm of the computer operating system may objectively determine the most advantageous order for the process threads to run and which of the processors in a multi-processor system should execute these process threads. A scoreboard register may be reassigned to a new process thread when its associated process thread has been discontinued.
Inventors
- 👤 E. David Neufeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:56
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0842; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/3471; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F9/4881; G06F9/50; G06F9/5005; G06F9/5027; G06F9/5033; G06F2201/00; G06F2201/88; G06F2201/885
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
188 words
A computer system having cached multi-thread processes, said system comprising: a processor; a cache memory connected to said processor, said cache memory having a plurality of memory lines; a main memory connected to said cache memory; a cache memory controller for transferring a predetermined number of bytes of information for active process threads from said main memory to said cache memory; a plurality of scoreboard registers, each of the active process threads assigned to corresponding ones of said plurality of scoreboard registers, wherein each of the corresponding ones of said plurality of scoreboard registers store a number value representing the number of said cache memory lines that contain information for each of the plurality of active process threads; logic circuits making available the number value in each of said plurality of scoreboard registers to a software operating system scheduler program, and logic circuits in said cache memory controller that identify certain ones of said cache memory lines that contain information for discontinued process threads so that these certain ones may be reused before other ones of said cache memory lines containing information for active process threads are reused.
Claim 2
Dependent Claim
188 words
A computer system having cached multi-thread processes, said system comprising: a processor; a cache memory connected to said processor, said cache memory having a plurality of memory lines; a main memory connected to said cache memory; a cache memory controller for transferring a predetermined number of bytes of information for active process threads from said main memory to said cache memory; a plurality of scoreboard registers, each of the active process threads assigned to corresponding ones of said plurality of scoreboard registers, wherein each of the corresponding ones of said plurality of scoreboard registers store a number value representing the number of said cache memory lines that contain information for each of the plurality of active process threads; logic circuits making available the number value in each of said plurality of scoreboard registers to a software operating system scheduler program, and logic circuits in said cache memory controller that identify certain ones of said cache memory lines that contain information for discontinued process threads so that these certain ones may be reused before other ones of said cache memory lines containing information for active process threads are reused.
Claim 3
Dependent Claim
48 words
The computer system of claim 1, wherein: said cache memory lines are identified by process thread identification numbers according to the process thread information stored therein; and said plurality of scoreboard registers being identified by the process thread identification numbers according to the active process threads assigned thereto.
Claim 4
Dependent Claim
14 words
The computer system of claim 1, wherein said processor is a plurality of processors.
Claim 5
Dependent Claim
16 words
The computer system of claim 1, wherein said cache memory is a plurality of cache memories.
Claim 6
Dependent Claim
37 words
The computer system of claim 4, wherein said cache memory controller is a plurality of cache memories controllers, each one of said plurality of cache memory controllers controlling a respective one of said plurality of cache memories.
Claim 7
Dependent Claim
26 words
The computer system of claim 1, wherein the certain ones of said cache memory lines are identified with a status bit in an associated tag block.
Claim 8
Dependent Claim
22 words
The computer system of claim 1, wherein said cache memory controller marks the certain ones of said cache memory lines as invalid.
Claim 9
Dependent Claim
25 words
The computer system of claim 2, further comprising a register containing the process thread identification number of the active process being executed by said processor.
Claim 10
Dependent Claim
30 words
The computer system of claim 1, wherein the number value in each of said plurality of scoreboard registers increments when information is stored in corresponding lines of said cache memory.
Claim 11
Dependent Claim
30 words
The computer system of claim 1, wherein the number value in each of said plurality of scoreboard registers decrements when information is deleted in corresponding lines of said cache memory.
Claim 12
Dependent Claim
41 words
The computer system of claim 1, wherein the number of predetermined bytes of information transferred to said cache memory lines is selected from the group of numbers consisting of 2 n where n is an integer number from 1 to 16.
Claim 13
Dependent Claim
72 words
The computer system of claim 1, further comprising: logic circuits for storing maximum number values representing the greatest number of said cache memory lines that contain information for each of the plurality of active process threads; and logic circuits for dividing the number values in each of said plurality of scoreboard registers by the maximum number values so as to normalize the number values into a percentage from 0 to 100 percent.
Claim 14
Dependent Claim
241 words
A multi-processor computer system having cached multi-thread processes, said system comprising: a plurality of processors; a plurality of cache memories, at least one of each of said plurality of cache memories associated with each of said plurality of processors, and each of said plurality of cache memories having a plurality of memory lines; a main memory connected to said plurality of cache memories; a plurality of cache memory controllers, one for each of said plurality of processors, said plurality of cache memory controllers transferring a predetermined number of bytes of information for active process threads from said main memory to said plurality of cache memories; a plurality of scoreboard registers, each of the active process threads assigned to corresponding ones of said plurality of scoreboard registers, wherein each of the corresponding ones of said plurality of scoreboard registers store a number value representing the number of the memory lines for each of said plurality of cache memories that contain information for each of the active process threads, wherein the number value stored in each of said plurality of scoreboard registers is available to a software operating system scheduler program, and logic circuits in each of said plurality of cache memory controllers that identify certain ones of said cache memory lines that contain information for discontinued process threads so that these certain ones may be reused before other ones of said cache memory lines containing information for active process threads are reused.
Claim 15
Dependent Claim
241 words
A multi-processor computer system having cached multi-thread processes, said system comprising: a plurality of processors; a plurality of cache memories, at least one of each of said plurality of cache memories associated with each of said plurality of processors, and each of said plurality of cache memories having a plurality of memory lines; a main memory connected to said plurality of cache memories; a plurality of cache memory controllers, one for each of said plurality of processors, said plurality of cache memory controllers transferring a predetermined number of bytes of information for active process threads from said main memory to said plurality of cache memories; a plurality of scoreboard registers, each of the active process threads assigned to corresponding ones of said plurality of scoreboard registers, wherein each of the corresponding ones of said plurality of scoreboard registers store a number value representing the number of the memory lines for each of said plurality of cache memories that contain information for each of the active process threads, wherein the number value stored in each of said plurality of scoreboard registers is available to a software operating system scheduler program, and logic circuits in each of said plurality of cache memory controllers that identify certain ones of said cache memory lines that contain information for discontinued process threads so that these certain ones may be reused before other ones of said cache memory lines containing information for active process threads are reused.
Claim 16
Dependent Claim
53 words
The computer system of claim 13, wherein: the memory lines of said plurality of cache memories are identified by process thread identification numbers according to the process thread information stored therein; and said plurality of scoreboard registers being identified by the process thread identification numbers according to the active process threads assigned thereto.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-25 | 2003-04-26 | 2003-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-25 | 2007-04-26 | 2007-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-25 | 2011-04-26 | 2011-10-26 | $7700.00 | Window Closed / Lapsed |