US5973368A
Expired / Lapsed
US
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Monolithic class D amplifier
Assignee: Intersil Americas LLC
•
Filing: 1996-06-05
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Granted: 1999-10-26
•
Expires: 2016-06-05
Abstract
Abstract A monolithic integrated circuit is mounted in a speaker cabinet to drive the voice coil of the speaker. The monolithic integrated circuit may be a class D amplifier and is at least a half bridge or full bridge power MOSFET device. Structures comprise MOS switching devices of the bridge driver and N+ buried layer of the QVDMOS transistors of the bridge circuits.
Inventors
- 👤 Lawrence G. Pearce
- 👤 Donald F. Hemmenway
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:23
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/52; H03F1/523; H03F3/00; H03F3/181; H03F3/183; H03F3/187; H03F3/20; H03F3/21; H03F3/217; H03F3/2171; H03F3/2173; H03F3/72; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D30/0293; H10D30/60; H10D30/64; H10D30/66; H10D30/663; H10D30/665; H10D30/669; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D89/00; H10D89/10; H10D30/0212; H10D62/102; H10D62/103; H10D62/105; H10D62/17; H10D62/393; H10D62/80; H10D62/83; H10D64/60; H10D64/62
Claims Analysis
Total Claims: 83
Claim 1
Independent Claim
187 words
In a substrate of semiconductor material, a monolithic integrated circuit for providing a class D amplifier function comprising: (a) a conditioning circuit having an input for receiving an audio input frequency signal and generating an output series of class D amplifier conditioning pulses representative of the amplitude and the frequency of the audio input signal, said output series of pulses having a frequency substantially greater than said audio frequency; (b) a bridge driver circuit having an input for receiving the output series of class D amplifier conditioning pulses and translating the voltage level of the pulses from the reference voltage to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level; (c) a bridge circuit comprising a plurality of power MOSFET devices for receiving the output power driving pulses from the bridge driver circuit, means for applying the power driver pulses to the gates of the power MOSFETs to generate output power voltage pulses at a power voltage level.
Claim 2
Dependent Claim
187 words
In a substrate of semiconductor material, a monolithic integrated circuit for providing a class D amplifier function comprising: (a) a conditioning circuit having an input for receiving an audio input frequency signal and generating an output series of class D amplifier conditioning pulses representative of the amplitude and the frequency of the audio input signal, said output series of pulses having a frequency substantially greater than said audio frequency; (b) a bridge driver circuit having an input for receiving the output series of class D amplifier conditioning pulses and translating the voltage level of the pulses from the reference voltage to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level; (c) a bridge circuit comprising a plurality of power MOSFET devices for receiving the output power driving pulses from the bridge driver circuit, means for applying the power driver pulses to the gates of the power MOSFETs to generate output power voltage pulses at a power voltage level.
Claim 3
Dependent Claim
89 words
The integrated circuit of claim 1 wherein the conditioning circuit comprises means for receiving an audio frequency input signal, means for sampling the audio input signal at a frequency substantially greater than the highest audio frequency in the audio input signal, and means for comparing the sampled audio signal to a reference voltage signal to provide an output series of class D amplifier conditioning width modulated pulses, each pulse having the amplitude of the reference voltage signal and a width proportional to the amplitude of the sampled audio signal.
Claim 4
Dependent Claim
77 words
The integrated circuit of claim 1 wherein the conditioning circuit comprises means for receiving an audio frequency input signal, means for sampling the audio input signal at a frequency substantially greater than the highest audio frequency in the audio input signal, and means for generating an output series of class D amplifier density modulated pulses, each pulse having the amplitude of the reference voltage signal and a density proportional to the amplitude of the sampled audio signal.
Claim 5
Dependent Claim
96 words
The integrated circuit of claim 1 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch, said power MOS switch comprising MOS transistors each MOS transistor comprising: (a) four drain regions spaced from each other; (b) a common gate enclosing the drain regions; and (c) a source region centrally located among the drain regions, said source region comprising a pair of elongated source distribution regions disposed transverse to each other, adjacent the common enclosing gate and between adjacent drain regions.
Claim 6
Dependent Claim
116 words
The integrated circuit of claim 4 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising an array of MOS transistors wherein said array comprises a waffle pattern of drain regions and gate regions and a source distribution region comprising: a central source distribution region having first and second elongated source distribution regions disposed transverse to each other and defining four quadrants, each quadrant disposed between a first and second source distribution region; four drain regions, one drain region being located in each quadrant; and one or more gate regions separating the drain regions from the source distribution regions.
Claim 7
Dependent Claim
16 words
The integrated circuit of claim 5 wherein a common gate region encloses all said drain regions.
Claim 8
Dependent Claim
28 words
The integrated circuit of claim 6 wherein the gate region extends at least between drain regions in quadrants on one side of one of the source distribution regions.
Claim 9
Dependent Claim
136 words
The integrated circuit of claim 1 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising: an array of MOS devices, said array comprising alternating drain columns and source columns; each drain column comprising a plurality of separate drain regions closely spaced one from another; each source column comprising a continuous narrow elongated source distribution region extending the length of the column and a plurality of narrow source distribution branch regions connected to said elongated region and extending transversely from said elongated region at least partially between each separate drain region in each drain column adjacent to said source column; and a gate region separating the drain regions in each said drain column from the adjacent source distribution regions.
Claim 10
Dependent Claim
13 words
The integrated circuit of claim 8 wherein said gate region comprises doped polysilicon.
Claim 11
Dependent Claim
15 words
The integrated circuit of claim 9 wherein said doped polysilicon comprises a self-aligned silicide layer.
Claim 12
Dependent Claim
23 words
The integrated circuit of claim 10 wherein said silicide layer comprises a silicide of a metal selected from platinum, titanium, cobalt, and tungsten.
Claim 13
Dependent Claim
11 words
The integrated circuit of claim 11 wherein said metal is platinum.
Claim 14
Dependent Claim
27 words
The integrated circuit of claim 8 wherein each source distribution region in each source column is interconnected with every other source distribution region in every other column.
Claim 15
Dependent Claim
20 words
The integrated circuit of claim 8 wherein each drain region in a drain column is encompassed by a gate region.
Claim 16
Dependent Claim
33 words
The integrated circuit of claim 14 wherein each gate region encompassing each drain region in a drain column is connected to each adjacent gate region in that drain column by a polysilicon bridge.
Claim 17
Dependent Claim
16 words
The integrated circuit of claim 15 wherein said polysilicon bridge comprises a self-aligned metal silicide layer.
Claim 18
Dependent Claim
16 words
The integrated circuit of claim 8 further comprising a drain contact situated within each drain region.
Claim 19
Dependent Claim
29 words
The integrated circuit of claim 17 further comprising a source contact situated in each of the areas of intersection of said elongated source distribution regions with said branch regions.
Claim 20
Dependent Claim
14 words
The integrated circuit of claim 8 wherein the drain regions have a silicide layer.
Claim 21
Dependent Claim
23 words
The integrated circuit of claim 19 wherein the silicide layer comprises a silicide selected from the group of platinum, titanium, cobalt, and tungsten.
Claim 22
Dependent Claim
14 words
The integrated circuit of claim 8 wherein the source regions have a silicide layer.
Claim 23
Dependent Claim
23 words
The integrated circuit of claim 21 wherein the silicide layer comprises a silicide selected from the group of platinum, titanium, cobalt, and tungsten.
Claim 24
Dependent Claim
167 words
The integrated circuit of claim 1 wherein each power MOSFET device in the bridge circuit comprises a quasi-vertical DMOS (QVDMOS) transistor, each QVDMOS transistor comprising: in the substrate a region having a first conductivity; a buried layer in said substrate of a second conductivity and heavily doped; an epitaxial layer of a second conductivity on said substrate and over said buried layer; a drain region extending from the surface of the epitaxial layer to the buried layer and having a second conductivity; a body region formed in the surface of the epitaxial layer, spaced from said drain region and having a first conductivity; a source region formed in said body region, having a shallow depth and having a second conductivity; a body tie formed in the source region, having a first conductivity, a depth slightly greater than the depth of the source region and extending under and not beyond the source region; a gate insulated from the epitaxial layer and extending over the source and body regions.
Claim 25
Dependent Claim
15 words
The integrated circuit of claim 23 wherein the QVDMOS transistor comprises an annular source region.
Claim 26
Dependent Claim
20 words
The integrated circuit of claim 23 wherein the QVDMOS transistor comprises a body tie disposed within the annular source region.
Claim 27
Dependent Claim
14 words
The integrated circuit of claim 23 wherein the source and body tie are silicided.
Claim 28
Dependent Claim
17 words
The integrated circuit of claim 23 wherein the source and body tie are self-aligned with the gate.
Claim 29
Dependent Claim
32 words
The integrated circuit of claim 23 wherein the gate comprises a dielectric layer in contact with the surface of the epitaxial layer and a conductive layer in contact with the dielectric layer.
Claim 30
Dependent Claim
39 words
The integrated circuit of claim 23 wherein the body tie and the source regions have a high conductivity and the body tie serves as a low resistance path between the body region and the surface of the epitaxial layer.
Claim 31
Dependent Claim
103 words
The integrated circuit of claim 1 wherein each power MOSFET device is a QVDMOS transistor comprising: a body region formed in the surface of the substrate and having a first conductivity; a source region formed in said body region, having a shallow depth and having a second conductivity; a body tie formed in the drain region, having a first conductivity, a depth slightly greater than the depth of the source region and extending under and not beyond the source region; a gate insulated from the epitaxial layer and extending over the source and body regions; and a drain region having a second conductivity.
Claim 32
Dependent Claim
15 words
The integrated circuit of claim 30 wherein the QVDMOS transistor comprises an annular source region.
Claim 33
Dependent Claim
20 words
The integrated circuit of claim 30 wherein the QVDMOS transistor comprises a body tie disposed within the annular source region.
Claim 34
Dependent Claim
14 words
The integrated circuit of claim 30 wherein the source and body tie are silicided.
Claim 35
Dependent Claim
17 words
The integrated circuit of claim 30 wherein the source and body tie are self-aligned with the gate.
Claim 36
Dependent Claim
32 words
The integrated circuit of claim 30 wherein the gate comprises a dielectric layer in contact with the surface of the epitaxial layer and a conductive layer in contact with the dielectric layer.
Claim 37
Dependent Claim
39 words
The integrated circuit of claim 30 wherein the body tie and the source regions have a high conductivity and the body tie serves as a low resistance path between the body region and the surface of the epitaxial layer.
Claim 38
Dependent Claim
109 words
The integrated circuit of claim 1 wherein each power MOSFET device comprises a QVDMOS transistor in the surface of a semiconductor substrate and having a drain spaced from a source, a buried layer in contact with the drain, a gate with an opening defining a body region, said body region disposed over the buried layer and comprising a source and body tie wherein the body region and the body tie are of a first conductivity and the source is of a second conductivity, the improvement comprising a body tie enclosed at the surface by the source and extending below the source radially outward and not beyond the source region.
Claim 39
Dependent Claim
14 words
The integrated circuit of claim 37 wherein the source and body tie are silicided.
Claim 40
Dependent Claim
71 words
The integrated circuit of claim 1 wherein the semiconductor substrate comprises monocrystalline semiconductor material having an epitaxial layer, said integrated circuit formed in the epitaxial layer, said epitaxial layer disposed on the substrate and over a buried layer, said buried layer comprising dopant ions of a size about the size of the atoms of the semiconductor material, said buried layer having a sheet resistance of less than 15 ohms per square.
Claim 41
Dependent Claim
21 words
The integrated circuit of claim 39 wherein the monocrystalline semiconductor substrate has a sheet resistance is about 6.5 ohms per square.
Claim 42
Dependent Claim
18 words
The integrated circuit of claim 39 wherein the semiconductor material is silicon and the buried layer comprises arsenic.
Claim 43
Dependent Claim
27 words
The integrated circuit of claim 39 wherein the depth of the buried layer is about 5.4 microns below an interface of the substrate and the epitaxial layer.
Claim 44
Dependent Claim
19 words
The integrated circuit of claim 39 wherein the lateral diffusion of the buried layer is less than six microns.
Claim 45
Dependent Claim
178 words
In a substrate of semiconductor material, a monolithic integrated circuit comprising: (a) a class D amplifier having an input for receiving a signal with an audio frequency, means for sampling the audio input signal at a frequency substantially greater than the highest audio frequency in the audio input signal, and means for comparing the sampled audio signal to a reference voltage signal to provide a output series of width modulated pulses, each pulse having the amplitude of the reference voltage signal and a width proportional to the amplitude of the sampled audio signal, the series of pulses having a frequency substantially greater than said audio frequency; and (b) a bridge driver circuit having an input for receiving the output series of pulses of the class D amplifier and translating the voltage level of the pulses from the reference voltage to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level.
Claim 46
Dependent Claim
178 words
In a substrate of semiconductor material, a monolithic integrated circuit comprising: (a) a class D amplifier having an input for receiving a signal with an audio frequency, means for sampling the audio input signal at a frequency substantially greater than the highest audio frequency in the audio input signal, and means for comparing the sampled audio signal to a reference voltage signal to provide a output series of width modulated pulses, each pulse having the amplitude of the reference voltage signal and a width proportional to the amplitude of the sampled audio signal, the series of pulses having a frequency substantially greater than said audio frequency; and (b) a bridge driver circuit having an input for receiving the output series of pulses of the class D amplifier and translating the voltage level of the pulses from the reference voltage to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level.
Claim 47
Dependent Claim
116 words
The integrated circuit of claim 44 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising an array of MOS transistors wherein said array comprises a waffle pattern of drain regions and gate regions and a source distribution region comprising: a central source distribution region having first and second elongated source distribution regions disposed transverse to each other and defining four quadrants, each quadrant disposed between a first and second source distribution region; four drain regions, one drain region being located in each quadrant; and one or more gate regions separating the drain regions from the source distribution regions.
Claim 48
Dependent Claim
16 words
The integrated circuit of claim 45 wherein a common gate region encloses all said drain regions.
Claim 49
Dependent Claim
28 words
The integrated circuit of claim 46 wherein the gate region extends at least between drain regions in quadrants on one side of one of the source distribution regions.
Claim 50
Dependent Claim
136 words
The integrated circuit of claim 44 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising: an array of MOS devices, said array comprising alternating drain columns and source columns; each drain column comprising a plurality of separate drain regions closely spaced one from another; each source column comprising a continuous narrow elongated source distribution region extending the length of the column and a plurality of narrow source distribution branch regions connected to said elongated region and extending transversely from said elongated region at least partially between each separate drain region in each drain column adjacent to said source column; and a gate region separating the drain regions in each said drain column from the adjacent source distribution regions.
Claim 51
Dependent Claim
129 words
In a substrate of semiconductor material, a monolithic integrated circuit comprising: (a) a bridge driver circuit having an input for receiving a series of class D amplifier conditioning pulses and translating the voltage level of the pulses from a first voltage level to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to-the sampled audio signal and pulse amplitudes at the driver voltage level; and (b) a bridge circuit comprising a plurality of power MOSFET devices for receiving the output power driving pulses from the bridge driver circuit, means for applying the power driver pulses to the gates of the power MOSFETs to generate output power voltage pulses at a power voltage level.
Claim 52
Dependent Claim
129 words
In a substrate of semiconductor material, a monolithic integrated circuit comprising: (a) a bridge driver circuit having an input for receiving a series of class D amplifier conditioning pulses and translating the voltage level of the pulses from a first voltage level to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to-the sampled audio signal and pulse amplitudes at the driver voltage level; and (b) a bridge circuit comprising a plurality of power MOSFET devices for receiving the output power driving pulses from the bridge driver circuit, means for applying the power driver pulses to the gates of the power MOSFETs to generate output power voltage pulses at a power voltage level.
Claim 53
Dependent Claim
116 words
The integrated circuit of claim 44 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising an array of MOS transistors wherein said array comprises a waffle pattern of drain regions and gate regions and a source distribution region comprising: a central source distribution region having first and second elongated source distribution regions disposed transverse to each other and defining four quadrants, each quadrant disposed between a first and second source distribution region; four drain regions, one drain region being located in each quadrant; and one or more gate regions separating the drain regions from the source distribution regions.
Claim 54
Dependent Claim
16 words
The integrated circuit of claim 50 wherein a common gate region encloses all said drain regions.
Claim 55
Dependent Claim
28 words
The integrated circuit of claim 51 wherein the gate region extends at least between drain regions in quadrants on one side of one of the source distribution regions.
Claim 56
Dependent Claim
136 words
The integrated circuit of claim 50 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising: an array of MOS devices, said array comprising alternating drain columns and source columns; each drain column comprising a plurality of separate drain regions closely spaced one from another; each source column comprising a continuous narrow elongated source distribution region extending the length of the column and a plurality of narrow source distribution branch regions connected to said elongated region and extending transversely from said elongated region at least partially between each separate drain region in each drain column adjacent to said source column; and a gate region separating the drain regions in each said drain column from the adjacent source distribution regions.
Claim 57
Dependent Claim
168 words
The integrated circuit of claim 50 wherein the power MOSFET devices in the bridge circuit comprise two or more quasi-vertical DMOS (QVDMOS) transistors, each QVDMOS transistor comprising: in the substrate region having a first conductivity; a buried layer in said substrate of a second conductivity and heavily doped; an epitaxial layer of a second conductivity on said substrate and over said buried layer; a drain region extending from the surface of the epitaxial layer to the buried layer and having a second conductivity; a body region formed in the surface of the epitaxial layer, spaced from said drain region and having a first conductivity; a source region formed in said body region, having a shallow depth and having a second conductivity; a body tie formed in the source region, having a first conductivity, a depth slightly greater than the depth of the source region and extending under and not beyond the source region; a gate insulated from the epitaxial layer and extending over the source and body regions.
Claim 58
Dependent Claim
15 words
The integrated circuit of claim 54 wherein the QVDMOS transistor comprises an annular source region.
Claim 59
Dependent Claim
20 words
The integrated circuit of claim 54 wherein the QVDMOS transistor comprises a body tie disposed within the annular source region.
Claim 60
Dependent Claim
14 words
The integrated circuit of claim 54 wherein the source and body tie are silicided.
Claim 61
Dependent Claim
17 words
The integrated circuit of claim 54 wherein the source and body tie are self-aligned with the gate.
Claim 62
Dependent Claim
32 words
The integrated circuit of claim 54 wherein the gate comprises a dielectric layer in contact with the surface of the epitaxial layer and a conductive layer in contact with the dielectric layer.
Claim 63
Dependent Claim
39 words
The integrated circuit of claim 54 wherein the body tie and the source regions have a high conductivity and the body tie serves as a low resistance path between the body region and the surface of the epitaxial layer.
Claim 64
Dependent Claim
102 words
The integrated circuit of claim 50 wherein each power MOSFET comprises a QVDMOS transistor comprising: a body region formed in the surface of the substrate and having a first conductivity; a source region formed in said body region, having a shallow depth and having a second conductivity; a body tie formed in the drain region, having a first conductivity, a depth slightly greater than the depth of the source region and extending under and not beyond the source region; a gate insulated from the epitaxial layer and extending over the source and body regions; and a drain region having a second conductivity.
Claim 65
Dependent Claim
15 words
The integrated circuit of claim 61 wherein the QVDMOS transistor comprises an annular source region.
Claim 66
Dependent Claim
20 words
The integrated circuit of claim 61 wherein the QVDMOS transistor comprises a body tie disposed within the annular source region.
Claim 67
Dependent Claim
14 words
The integrated circuit of claim 61 wherein the source and body tie are silicided.
Claim 68
Dependent Claim
17 words
The integrated circuit of claim 61 wherein the source and body tie are self-aligned with the gate.
Claim 69
Dependent Claim
32 words
The integrated circuit of claim 61 wherein the gate comprises a dielectric layer in contact with the surface of the epitaxial layer and a conductive layer in contact with the dielectric layer.
Claim 70
Dependent Claim
39 words
The integrated circuit of claim 61 wherein the body tie and the source regions have a high conductivity and the body tie serves as a low resistance path between the body region and the surface of the epitaxial layer.
Claim 71
Dependent Claim
109 words
The integrated circuit of claim 50 wherein each power MOSFET device comprises a QVDMOS transistor in the surface of a semiconductor substrate and having a drain spaced from a source, a buried layer in contact with the drain, a gate with an opening defining a body region, said body region disposed over the buried layer and comprising a source and body tie wherein the body region and the body tie are of a first conductivity and the source is of a second conductivity, the improvement comprising a body tie enclosed at the surface by the source and extending below the source radially outward and not beyond the source region.
Claim 72
Dependent Claim
14 words
The integrated circuit of claim 68 wherein the source and body tie are silicided.
Claim 73
Dependent Claim
71 words
The integrated circuit of claim 50 wherein the semiconductor substrate comprises monocrystalline semiconductor material having an epitaxial layer, said integrated circuit formed in the epitaxial layer, said epitaxial layer disposed on the substrate and over a buried layer, said buried layer comprising dopant ions of a size about the size of the atoms of the semiconductor material, said buried layer having a sheet resistance of less than 15 ohms per square.
Claim 74
Dependent Claim
21 words
The integrated circuit of claim 70 wherein the monocrystalline semiconductor substrate has a sheet resistance is about 6.5 ohms per square.
Claim 75
Dependent Claim
18 words
The integrated circuit of claim 70 wherein the semiconductor material is silicon and the buried layer comprises arsenic.
Claim 76
Dependent Claim
27 words
The integrated circuit of claim 70 wherein the depth of the buried layer is about 5.4 microns below an interface of the substrate and the epitaxial layer.
Claim 77
Dependent Claim
19 words
The integrated circuit of claim 70 wherein the lateral diffusion of the buried layer is less than six microns.
Claim 78
Dependent Claim
190 words
In a substrate of semiconductor material, a monolithic integrated circuit comprising: a bridge driver circuit having an input for receiving a series of class D amplifier conditioning pulses and translating the voltage level of the pulses from a first voltage level to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level wherein said bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising an array of MOS transistors wherein said array comprises a waffle pattern of drain regions and gate regions and a source distribution region comprising: a central source distribution region having first and second elongated source distribution regions disposed transverse to each other and defining four quadrants, each quadrant disposed between a first and second source distribution region; four drain regions, one drain region being located in each quadrant; and one or more gate regions separating the drain regions from the source distribution regions.
Claim 79
Dependent Claim
190 words
In a substrate of semiconductor material, a monolithic integrated circuit comprising: a bridge driver circuit having an input for receiving a series of class D amplifier conditioning pulses and translating the voltage level of the pulses from a first voltage level to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level wherein said bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising an array of MOS transistors wherein said array comprises a waffle pattern of drain regions and gate regions and a source distribution region comprising: a central source distribution region having first and second elongated source distribution regions disposed transverse to each other and defining four quadrants, each quadrant disposed between a first and second source distribution region; four drain regions, one drain region being located in each quadrant; and one or more gate regions separating the drain regions from the source distribution regions.
Claim 80
Dependent Claim
16 words
The integrated circuit of claim 75 wherein a common gate region encloses all said drain regions.
Claim 81
Dependent Claim
28 words
The integrated circuit of claim 75 wherein the gate region extends at least between drain regions in quadrants on one side of one of the source distribution regions.
Claim 82
Dependent Claim
195 words
In a substrate of semiconductor material, a monolithic integrated circuit comprising bridge driver circuit having an input for receiving the output series of pulses of a class D amplifier and translating the voltage level of the pulses from a first voltage level to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level wherein said bridge driver circuit comprises a power MOS switch comprising: an array of MOS devices, said array comprising alternating drain columns and source columns; each drain column comprising a plurality of separate drain regions closely spaced one from another; each source column comprising a continuous narrow elongated source distribution region extending the length of the column and a plurality of narrow source distribution branch regions connected to said elongated region and extending transversely from said elongated region at least partially between each separate drain region in each drain column adjacent to said source column; and a gate region separating the drain regions in each said drain column from the adjacent source distribution regions.
Claim 83
Dependent Claim
195 words
In a substrate of semiconductor material, a monolithic integrated circuit comprising bridge driver circuit having an input for receiving the output series of pulses of a class D amplifier and translating the voltage level of the pulses from a first voltage level to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level wherein said bridge driver circuit comprises a power MOS switch comprising: an array of MOS devices, said array comprising alternating drain columns and source columns; each drain column comprising a plurality of separate drain regions closely spaced one from another; each source column comprising a continuous narrow elongated source distribution region extending the length of the column and a plurality of narrow source distribution branch regions connected to said elongated region and extending transversely from said elongated region at least partially between each separate drain region in each drain column adjacent to said source column; and a gate region separating the drain regions in each said drain column from the adjacent source distribution regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-25 | 2003-04-26 | 2003-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-25 | 2007-04-26 | 2007-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-25 | 2011-04-26 | 2011-10-26 | $7700.00 | Window Closed / Lapsed |