DC offset and gain correction for CMOS image sensor

Claim 3

The method of claim 1, wherein step (c) comprises the steps of: (1) applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and (2) applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value.

Claim 4

The method of claim 1, wherein step (c) comprises the steps of: (1) applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine a current reference dc offset value; (2) applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating a current reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value; (3) determining the reference dc offset value by calculating a running average of the current reference dc offset value and a plurality of previous reference dc offset values; and (4) determining the reference gain value by calculating a running average of the current gain offset value and a plurality of previous reference gain values.

Claim 5

The method of claim 1, further comprising the step of repeating steps (c)-(f) for each vertical blanking period.

Claim 6

The method of claim 1, wherein each of the plurality of gain correction coefficients and dc offset correction coefficients have an initial value of zero before being updated in step (f).

Claim 7

The method of claim 1, wherein: step (e) comprises the step of computing the sign of the differences between the dc offset value and gain value for each CDS circuit and the reference dc offset value and reference gain value, respectively; and step (f) comprises the step of incrementing or decrementing each correction coefficient by a step size in accordance with the sign of the difference corresponding to said each correction coefficient.

Claim 8

The method of claim 6, wherein the step size is small enough to change a correction coefficient by an amount less than the that caused by random noise.

Claim 9

The method of claim 1, wherein the reference dc offset value and reference gain value are determined with respect to a reference CDS circuit, wherein the reference CDS circuit is the first CDS circuit of the row of CDS circuits.

Claim 10

An imaging system providing means for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the imaging system comprising: (a) memory means for storing a plurality of gain correction coefficients, one for each CDS circuit and a plurality of dc offset correction coefficients, one for each CDS circuit; (b) means for determining a reference dc offset value and a reference gain value; (c) means for measuring an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output; (d) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit; (e) means for updating the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit; and (f) a correction circuit for correcting the output of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattem noise in the row of CDS circuits.

Claim 11

An imaging system providing means for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the imaging system comprising: (a) memory means for storing a plurality of gain correction coefficients, one for each CDS circuit and a plurality of dc offset correction coefficients, one for each CDS circuit; (b) means for determining a reference dc offset value and a reference gain value; (c) means for measuring an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output; (d) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit; (e) means for updating the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit; and (f) a correction circuit for correcting the output of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattem noise in the row of CDS circuits.

Claim 12

The imaging system of claim 9, wherein means (b) comprises: (1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and (2) means for applying a full well signal to the input of the reference CDS circuit and measuring a fall well output value output by the reference CDS circuit to determine a reference full well output value and for calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference fill well output value.

Claim 13

The imaging system of claim 9, wherein means (b) comprises: (1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine a current reference dc offset value; (2) means for applying a full well signal to the input of a reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference fall well output value and for calculating a current reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value; (3) means for determining the reference dc offset value by calculating a running average of the current reference dc offset value and a plurality of previous reference dc offset values; and (4) means for determining the reference gain value by calculating a running average of the current gain offset value and a plurality of previous reference gain values.

Claim 14

The imaging system of claim 9, further comprising means for repeating the functions of means (b)-(e) for each vertical blanking period.

Claim 15

The imaging system of claim 9, wherein each of the plurality of gain correction coefficients and dc offset correction coefficients have an initial value of zero before being updated in step (f).

Claim 16

The imaging system of claim 9, wherein: means (d) comprises means for computing the sign of the differences between the dc offset value d gain value for each CDS circuit and the reference dc offset value and reference gain value, respectively; and means (e) comprises means for incrementing or decrementing each correction coefficient by a step size in accordance with the sign of the difference corresponding to said each correction coefficient.

Claim 17

The imaging system of claim 14, wherein the step size is small enough to change a correction coefficient by an amount less than the that caused by random noise.

Claim 18

The imaging system of claim 9, wherein the reference dc offset value and reference gain value are determined with respect to a reference CDS circuit, wherein the reference CDS circuit is the first CDS circuit of the row of CDS circuits.

Claim 19

An imaging system, comprising: (1) a row of CDS circuits for sampling output signals provided by pixel circuits of an array of pixel sensor circuits; and (2) a processor coupled to input, output, and control lines of each CDS circuit of the row of CDS circuits, wherein the processor: (a) stores a plurality of gain correction coefficients, one for each CDS circuit; (b) stores a plurality of dc offset correction coefficients, one for each CDS circuit; (c) determines a reference dc offset value and a reference gain value; (d) measures an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output; (e) compares the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit; (f) updates the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit; and (g) corrects, with a correction circuit, the outut of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattern noise in the row of CDS circuits.

Claim 20

An imaging system, comprising: (1) a row of CDS circuits for sampling output signals provided by pixel circuits of an array of pixel sensor circuits; and (2) a processor coupled to input, output, and control lines of each CDS circuit of the row of CDS circuits, wherein the processor: (a) stores a plurality of gain correction coefficients, one for each CDS circuit; (b) stores a plurality of dc offset correction coefficients, one for each CDS circuit; (c) determines a reference dc offset value and a reference gain value; (d) measures an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output; (e) compares the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit; (f) updates the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit; and (g) corrects, with a correction circuit, the outut of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattern noise in the row of CDS circuits.

Claim 21

The imaging system of claim 17, wherein the processor determines a reference dc offset value and a reference gain value by: applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and applying a full well signal to the input of a reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value.

Claim 22

The imaging system of claim 17, wherein the processor determines a reference dc offset value and a reference gain value by: applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine a current reference dc offset value; applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating a current reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value; determining the reference dc offset value by calculating a running average of the current reference dc offset value and a plurality of previous reference dc offset values; and determining the reference gain value by calculating a running average of the current gain offset value and a plurality of previous reference gain values.

Claim 23

The imaging system of claim 17, wherein the processor repeats functions (c)-(f) for each vertical blanking period.

Claim 24

The imaging system of claim 17, wherein each of the plurality of gain correction coefficients and dc offset correction coefficients have an initial value of zero before being updated in step (f).

Claim 25

The imaging system of claim 17, wherein the processor updates the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons by incrementing or decrementing each correction coefficient by a step size in accordance with the sign of said differences, respectively.

Claim 26

The imaging system of claim 22, wherein the step size is small enough to change a correction coefficient by an amount less than the that caused by random noise.

Claim 27

The imaging system of claim 17, wherein the reference dc offset value and reference gain value are determined with respect to a reference CDS circuit, wherein the reference CDS circuit is the first CDS circuit of the row of CDS circuits.

Claim 28

An imaging system comprising: (a) a row of CDS circuits; (b) memory means for storing a plurality of gain correction coefficients, one for each CDS circuit, and a plurality of dc offset correction coefficients, one for each CDS circuit; (c) means for determining a reference dc offset value and a reference gain value; (d) means for measuring an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output; (e) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit; (f) means for updating the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit; and (g) a correction circuit for correcting the output of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattern noise in the row of CDS circuits.

Claim 29

An imaging system comprising: (a) a row of CDS circuits; (b) memory means for storing a plurality of gain correction coefficients, one for each CDS circuit, and a plurality of dc offset correction coefficients, one for each CDS circuit; (c) means for determining a reference dc offset value and a reference gain value; (d) means for measuring an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output; (e) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit; (f) means for updating the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit; and (g) a correction circuit for correcting the output of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattern noise in the row of CDS circuits.

Claim 32

An imaging system providing means for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the imaging system comprising: (a) memory means for storing a plurality of gain correction coefficients having an initial value and a plurality of dc offset correction coefficients having an initial value; (b) means for determining a reference dc offset value and a reference gain value, said means comprising: (1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and (2) means for applying a fall well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and for calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value; (c) means for determining an actual dc offset value and an actual gain value for each CDS circuit; (d) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively; and (e) means for updating the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

Claim 33

An imaging system providing means for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the imaging system comprising: (a) memory means for storing a plurality of gain correction coefficients having an initial value and a plurality of dc offset correction coefficients having an initial value; (b) means for determining a reference dc offset value and a reference gain value, said means comprising: (1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and (2) means for applying a fall well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and for calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value; (c) means for determining an actual dc offset value and an actual gain value for each CDS circuit; (d) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively; and (e) means for updating the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

Claim 34

An imaging system, comprising: (1) a row of CDS circuits for sampling output signals provided by pixel circuits of an array of pixel sensor circuits; and (2) a processor coupled to input, output, and control lines of each CDS circuit of the row of CDS circuits, wherein the processor: (a) stores a plurality of gain correction coefficients having an initial value; (b) stores a plurality of dc offset correction coefficients having an initial value; (c) determines a reference dc offset value and a reference gain value by: applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and applying a full well signal to the input of a reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value; (d) determines an actual dc offset value and an actual gain value for each CDS circuit; (e) compares the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively; and (f) updates the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

Claim 35

An imaging system, comprising: (1) a row of CDS circuits for sampling output signals provided by pixel circuits of an array of pixel sensor circuits; and (2) a processor coupled to input, output, and control lines of each CDS circuit of the row of CDS circuits, wherein the processor: (a) stores a plurality of gain correction coefficients having an initial value; (b) stores a plurality of dc offset correction coefficients having an initial value; (c) determines a reference dc offset value and a reference gain value by: applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and applying a full well signal to the input of a reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value; (d) determines an actual dc offset value and an actual gain value for each CDS circuit; (e) compares the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively; and (f) updates the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

Claim 36

An imaging system comprising: (a) a row of CDS circuits; (b) memory means for storing a plurality of gain correction coefficients having an initial value and a plurality of dc offset correction coefficients having an initial value; (c) means for determining a reference dc offset value and a reference gain value, said means comprising: (1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and (2) means for applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and for calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value; (d) means for determining an actual dc offset value and an actual gain value for each CDS circuit; (e) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively; and (f) means for updating the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

Claim 37

An imaging system comprising: (a) a row of CDS circuits; (b) memory means for storing a plurality of gain correction coefficients having an initial value and a plurality of dc offset correction coefficients having an initial value; (c) means for determining a reference dc offset value and a reference gain value, said means comprising: (1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and (2) means for applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and for calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value; (d) means for determining an actual dc offset value and an actual gain value for each CDS circuit; (e) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively; and (f) means for updating the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.