Optimized FIFO memory

Claim 2

A graphics processor having an internal storage unit for rendering graphics primitives, the graphics processor comprising: a bus interface unit for fetching display list instructions representing graphics primitives from an external memory source, said bus interface unit including bus-mastering circuitry to allow the graphics processor to bus-master an external system bus coupled to the graphics processor, said bus interface unit further comprising an address decoding means for decoding commands to determine whether to write commands and data to the internal storage unit; an internal storage unit coupled to the bus interface unit for internally storing pre-fetched graphics primitive data to be processed in the graphics processor, said internal storage unit comprising a plurality of registers for storing commands and data from said pre-fetched graphics primitive data, wherein the plurality of registers are First-In-First-Out (FIFO) registers and wherein data first received in the plurality of registers is first written out of the plurality of registers; an execution unit coupled to the bus interface unit and the internal storage unit to process the graphics primitive data; a bypass logic device coupled to the bus interface unit to selectively pass the graphics primitive data to the internal storage unit and the execution unit wherein if the bus interface unit detects an ongoing processing of commands and data stored in the internal storage unit, any incoming fetched graphics primitive data in the graphics processor are written directly to the execution unit; and a polygon engine for rendering graphics objects representing the graphics primitive data fetched from the external memory source.

Claim 3

The graphics processor of claim 1, wherein the bypass logic circuit includes a resume logic circuit to resume command and data writes to the internal storage unit after the internal storage unit is emptied of data by the execution unit.

Claim 4

A computer system comprising: a system bus for communicating data and commands; a host processor coupled to the system bus for processing the commands and data, the processor generating a display list of graphics primitive parameter data for graphics primitives; a system memory coupled to the system bus for storing the display list of graphics primitive parameter data; and a graphics processor coupled to the system bus, said graphics processor comprising: a bus interface unit for fetching the display list of graphics primitive parameter data from the system memory, the bus interface unit providing the graphics processor with bus-mastering capabilities to bus-master the system bus, said bus interface unit further comprising an address decoding means for decoding commands to determine whether to write commands and data to the internal storage unit; an internal storage unit coupled to the bus interface unit for storing the fetched display list of graphics primitive parameter data from the system memory, said internal storage unit comprising a plurality of registers for storing commands and data from said pre-fetched graphics primitive data, wherein the plurality of registers are First-In-First-Out (FIFO) registers and wherein data first received in the plurality of registers is first written out of the plurality of registers; an execution unit coupled to the bus interface unit and the internal storage unit to process the graphics primitive data; a bypass logic device coupled to the bus interface unit to selectively pass the graphics primitive data to the internal storage unit and the execution unit wherein if the bus interface unit detects an ongoing processing of commands and data stored in the internal storage unit, any incoming fetched graphics primitive data in the graphics processor are written directly to the execution unit; and a polygon engine for rendering graphics objects representing the graphics primitive data fetched from the system memory.

Claim 5

A computer system comprising: a system bus for communicating data and commands; a host processor coupled to the system bus for processing the commands and data, the processor generating a display list of graphics primitive parameter data for graphics primitives; a system memory coupled to the system bus for storing the display list of graphics primitive parameter data; and a graphics processor coupled to the system bus, said graphics processor comprising: a bus interface unit for fetching the display list of graphics primitive parameter data from the system memory, the bus interface unit providing the graphics processor with bus-mastering capabilities to bus-master the system bus, said bus interface unit further comprising an address decoding means for decoding commands to determine whether to write commands and data to the internal storage unit; an internal storage unit coupled to the bus interface unit for storing the fetched display list of graphics primitive parameter data from the system memory, said internal storage unit comprising a plurality of registers for storing commands and data from said pre-fetched graphics primitive data, wherein the plurality of registers are First-In-First-Out (FIFO) registers and wherein data first received in the plurality of registers is first written out of the plurality of registers; an execution unit coupled to the bus interface unit and the internal storage unit to process the graphics primitive data; a bypass logic device coupled to the bus interface unit to selectively pass the graphics primitive data to the internal storage unit and the execution unit wherein if the bus interface unit detects an ongoing processing of commands and data stored in the internal storage unit, any incoming fetched graphics primitive data in the graphics processor are written directly to the execution unit; and a polygon engine for rendering graphics objects representing the graphics primitive data fetched from the system memory.

Claim 6

The computer system of claim 3, wherein the bypass logic circuit includes a resume logic circuit to resume command and data writes to the internal storage unit after the internal storage unit is emptied of data by the execution unit.

Claim 7

The computer system of claim 4, wherein the bypass logic circuit includes a stalling logic device to stall command writes to the internal storage unit until data associated with the commands already stored in the internal storage unit have been fetched from the system memory.

Claim 8

The computer system of claim 5, wherein the graphics processor further includes an add logic device coupled to the bus interface unit and the internal storage unit to count the number of internal storage locations being written with commands.

Claim 9

The computer system of claim 5, wherein the internal storage unit comprises a plurality of First-In-First-Out registers and wherein each of said plurality of registers is six bits wide.

Claim 10

A graphics primitive storage bypass system for selectively storing graphics primitive parameter data internally in a graphics processor comprising: an address command register disposed within a graphics primitive bus interface unit; a decoding device coupled to the address command register to receive and decode the commands provided in the graphics primitive parameter data; a bypass device coupled to the decoding circuit to selectively determine where to write the pre-fetched commands internally in the graphics processor; and a adder device coupled to the bypass device for counting the number of storage locations in the internal storage unit storing commands pre-fetched to be processed in the graphics processor, said bypass device being selectively operable for detecting when ongoing processing of the stored commands is continuing, said graphics primitive storage bypass system being selectively operable for directly writing incoming pre-fetched graphics primitive parameter data to an execution unit of said graphics processor when ongoing processing of commands and data stored in said internal storage unit is detected.

Claim 11

A graphics primitive storage bypass system for selectively storing graphics primitive parameter data internally in a graphics processor comprising: an address command register disposed within a graphics primitive bus interface unit; a decoding device coupled to the address command register to receive and decode the commands provided in the graphics primitive parameter data; a bypass device coupled to the decoding circuit to selectively determine where to write the pre-fetched commands internally in the graphics processor; and a adder device coupled to the bypass device for counting the number of storage locations in the internal storage unit storing commands pre-fetched to be processed in the graphics processor, said bypass device being selectively operable for detecting when ongoing processing of the stored commands is continuing, said graphics primitive storage bypass system being selectively operable for directly writing incoming pre-fetched graphics primitive parameter data to an execution unit of said graphics processor when ongoing processing of commands and data stored in said internal storage unit is detected.

Claim 12

The graphics primitive storage bypass system of claim 8, further comprising: a stall device disposed in the bus interface unit to stall the writing of fetched graphics primitive parameter data to the internal storage unit while pre-fetched commands are being processed in the graphics processor.

Claim 13

The graphics primitive storage bypass system of claim 9, wherein one bit data values are set to indicate whether to bypass internally storing data in the graphics processor.

Claim 14

The graphics primitive storage bypass system of claim 10, wherein the bypass device comprises a one bit wide register.

Claim 15

The graphics primitive storage bypass system of claim 11, wherein the bypass device is set to resume command and data writes to the internal storage unit after the internal storage unit is bypassed by a previous data storage operation in the graphics processor.

Claim 18

The method of claim 13, and further including stalling storing commands in display list of graphics primitive parameter data internally in the graphics processor.

Claim 19

The method of claim 14, and further including resuming storing of commands internally in the graphics processor when ongoing processing of commands and data stored in said internal storage unit is terminated.