US5962930A
Expired / Lapsed
US
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Method and apparatus for detecting supply power loss
Assignee: Intel Corp
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Filing: 1997-11-26
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Granted: 1999-10-05
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Expires: 2017-11-26
Abstract
Abstract A microprocessor system includes a microprocessor and a first controller. The first controller is coupled to the microprocessor, and the first controller includes a first memory adapted to store a power loss indicator. A method for detecting a reduction of a power supply voltage in a microprocessor system includes coupling the power supply voltage to a first memory of a controller. A power loss indicator is stored in the first memory. The occurrence of a predetermined event is detected, and the first memory is read in response to the predetermined event to determine if the power loss indicator is intact.
Inventors
- 👤 Dean K. Cluff
- 👤 Loc Van Doan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:50
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/30
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
74 words
A microprocessor system, comprising: (a) a microprocessor; and (b) a first controller coupled to the microprocessor, the first controller including a first memory, wherein (i) the contents of the first memory are set to a specified value prior to a power interruption, and (ii) the microprocessor is adapted to read the memory and to determine if power has been interrupted by determining whether the contents of the memory are equal to the specified value.
Claim 2
Dependent Claim
74 words
A microprocessor system, comprising: (a) a microprocessor; and (b) a first controller coupled to the microprocessor, the first controller including a first memory, wherein (i) the contents of the first memory are set to a specified value prior to a power interruption, and (ii) the microprocessor is adapted to read the memory and to determine if power has been interrupted by determining whether the contents of the memory are equal to the specified value.
Claim 3
Dependent Claim
29 words
The microprocessor system of claim 1, further comprising a power supply adapted to provide a power supply voltage, wherein the power supply voltage is coupled to the first memory.
Claim 4
Dependent Claim
17 words
The microprocessor system of claim 1, wherein the first memory comprises a complimentary metal oxide silicon memory.
Claim 5
Dependent Claim
27 words
The microprocessor system of claim 1, wherein the microprocessor is adapted to store the specified value in the first memory during an initialization of the microprocessor system.
Claim 6
Dependent Claim
42 words
The microprocessor system of claim 1, further comprising: (c) a second controller coupled to the microprocessor, the second controller including a second memory adapted to store setup information related to the microprocessor system; and (d) a battery coupled to the second memory.
Claim 7
Dependent Claim
22 words
The microprocessor system of claim 5, wherein at least one of the first controller and the second controller comprises a bridge controller.
Claim 8
Dependent Claim
22 words
The microprocessor system of claim 5, wherein at least one of the first controller and the second controller comprises an input/output controller.
Claim 9
Dependent Claim
48 words
The microprocessor system of claim 1, wherein the microprocessor is adapted (i) to operate the microprocessor system in an off mode, and (ii) to read the memory and to determine whether the contents of the memory are equal to the specified value when exiting from the off mode.
Claim 10
Dependent Claim
23 words
The microprocessor system of claim 8, wherein the off mode comprises at least one of a softoff mode and a mechanical off mode.
Claim 11
Dependent Claim
50 words
The microprocessor system of claim 8, wherein the microprocessor is further adapted (i) to operate the microprocessor system in a full on mode, and (ii) to transition from the off mode to one of the full on mode and the off mode depending on the contents of the first memory.
Claim 12
Dependent Claim
78 words
The microprocessor system of claim 10, further comprising a second controller coupled to the microprocessor, the second controller including a second memory adapted to store setup information related to the microprocessor system, wherein the setup information includes a power interruption recovery option, and the microprocessor is adapted to transition from the off mode to one of the full on mode and the off mode depending on the contents of the first memory and the power interruption recovery option.
Claim 13
Independent Claim
101 words
A method for detecting a specified reduction of a power supply voltage in a microprocessor system, comprising: (a) providing a first memory that (i) is operatively coupled to the power supply voltage, and (ii) contains a specified value during normal, powered operation, wherein the specified reduction of the power supply voltage would be expected to result in a different value being contained in the first memory; (b) detecting the occurrence of a predetermined event; (c) reading the first memory in response to the predetermined event; and (d) determining if the contents of the first memory are equal to the specified value.
Claim 14
Independent Claim
101 words
A method for detecting a specified reduction of a power supply voltage in a microprocessor system, comprising: (a) providing a first memory that (i) is operatively coupled to the power supply voltage, and (ii) contains a specified value during normal, powered operation, wherein the specified reduction of the power supply voltage would be expected to result in a different value being contained in the first memory; (b) detecting the occurrence of a predetermined event; (c) reading the first memory in response to the predetermined event; and (d) determining if the contents of the first memory are equal to the specified value.
Claim 15
Dependent Claim
16 words
The method of claim 12, wherein the detecting includes detecting a reset of the microprocessor system.
Claim 16
Dependent Claim
17 words
The method of claim 12, wherein the detecting includes determining that a specified time interval has elapsed.
Claim 17
Dependent Claim
30 words
The method of claim 12, the microprocessor system being adapted to operate in an off mode, wherein the detecting includes determining that the microprocessor system is exiting the off mode.
Claim 18
Dependent Claim
28 words
The method of claim 12, further comprising storing setup information related to the microprocessor system in a second memory, the setup information including a power interruption recovery option.
Claim 19
Dependent Claim
64 words
The method of claim 16, the microprocessor system being adapted to operate in an off mode and a full on mode, the method further comprising: (1) determining that the microprocessor system is exiting the off mode; and (2) transitioning to one of the off mode and the full on mode depending on the contents of the first memory and the power interruption recovery option.
Claim 20
Dependent Claim
115 words
A microprocessor system, comprising: (a) a microprocessor; (b) a first controller coupled to the microprocessor, the first controller including a first memory, wherein (i) the contents of the first memory are set to a specified value prior to a power interruption, and (ii) the microprocessor is adapted to read the first memory to determine if power has been interrupted; (c) a power supply adapted to provide a power supply voltage, wherein the power supply voltage is coupled to the first memory; (d) a second controller coupled to the microprocessor, the second controller including a second memory adapted to store setup information related to the microprocessor system; and (e) a battery coupled to the second memory.
Claim 21
Dependent Claim
115 words
A microprocessor system, comprising: (a) a microprocessor; (b) a first controller coupled to the microprocessor, the first controller including a first memory, wherein (i) the contents of the first memory are set to a specified value prior to a power interruption, and (ii) the microprocessor is adapted to read the first memory to determine if power has been interrupted; (c) a power supply adapted to provide a power supply voltage, wherein the power supply voltage is coupled to the first memory; (d) a second controller coupled to the microprocessor, the second controller including a second memory adapted to store setup information related to the microprocessor system; and (e) a battery coupled to the second memory.
Claim 22
Independent Claim
50 words
A method, executed by a microprocessor, for detecting the occurrence of a power interruption, comprising: (a) storing a specified value in a memory prior to the power interruption; (b) determining whether the contents of the memory are equal to the specified value, and if not, then executing a power-interruption response.
Claim 23
Independent Claim
50 words
A method, executed by a microprocessor, for detecting the occurrence of a power interruption, comprising: (a) storing a specified value in a memory prior to the power interruption; (b) determining whether the contents of the memory are equal to the specified value, and if not, then executing a power-interruption response.
Claim 24
Dependent Claim
28 words
A program storage device encoding instructions, executable by the microprocessor of a specified one of claims 12 through 19, to perform the operations recited in the specified claim.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-04 | 2003-04-05 | 2003-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-04 | 2007-04-05 | 2007-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-04 | 2011-04-05 | 2011-10-05 | $7700.00 | Window Closed / Lapsed |