Abstract A high density transistor component and its manufacturing method which includes the steps of forming a pad oxide layer above a silicon substrate, forming a dielectric layer above the pad oxide layer, and growing an epitaxial silicon layer above the pad oxide layer covering the pad oxide layer as well as the dielectric layer. Source/drain regions including the heavily doped source/drain and the lightly doped source/drain are formed in the epitaxial silicon layer, and a gate terminal region composed from an assembly of a gate oxide layer, a gate terminal and two spacers is formed above the epitaxial silicon layer. The channel is located in the spatial location between the dielectric layer, the gate region and the source/drain regions.
A high density transistor component, comprising a semiconductor substrate; an epitaxial silicon layer formed above the substrate; a gate terminal formed above the silicon layer; two source/drain regions, each region located on each side of the gate terminal in the silicon layer; a channel region formed between the two source/drain regions, the channel region being smaller than about 0.18 μm in length; a dielectric layer formed underneath the channel region an oxide layer directly between the dielectric layer and the semiconductor substrate.
Claim 2
Dependent Claim
82 words
A high density transistor component, comprising a semiconductor substrate; an epitaxial silicon layer formed above the substrate; a gate terminal formed above the silicon layer; two source/drain regions, each region located on each side of the gate terminal in the silicon layer; a channel region formed between the two source/drain regions, the channel region being smaller than about 0.18 μm in length; a dielectric layer formed underneath the channel region an oxide layer directly between the dielectric layer and the semiconductor substrate.
Claim 3
Dependent Claim
19 words
A transistor component according to claim 1, wherein the dielectric layer comprises silicon nitride (Si 3 N 4 ).
Claim 4
Dependent Claim
18 words
A transistor component according to claim 2, wherein the thickness of the dielectric layer is about 1500˜3000 Å.
Claim 5
Dependent Claim
17 words
A transistor component according to claim 1, wherein the source/drain regions have a lightly doped drain structure.
Claim 6
Dependent Claim
21 words
A transistor component according to claim 1, wherein the gate terminal comprises a stacked gate oxide layer and a polysilicon layer.