Method and test site to monitor alignment shift and buried contact trench formation

Claim 1

A method of monitoring buried contact trench formation, comprising: providing a silicon integrated circuit wafer having chip regions with edges, test site regions, and a plurality of buried contact regions formed of active regions in said chip regions of said wafer; forming a first number of parallel first test electrodes on said integrated circuit wafer in each of said test site regions, wherein said parallel first test electrodes are formed by field isolation of active regions in said test site regions and are connected in series; forming a layer of gate oxide on said integrated circuit wafer, wherein said layer of gate oxide covers said chip regions and said test site regions; forming contact holes in said layer of gate oxide directly over each of said buried contact regions; forming a second number of test holes in said layer of gate oxide directly over each of said first test electrodes, wherein said test holes have the same size and shape as said contact holes and are formed at the same time said contact holes are formed; forming buried contacts through said contact holes in said buried contact regions; forming a layer of first conductor material on said layer of gate oxide after etching said contact holes and said test holes in said layer of gate oxide; forming a photoresist mask on said layer of first conductor material; forming contact electrodes and gate electrodes in said layer of first conductor material using said photoresist mask, dry anisotropic etching of said conductor material, and said layer of gate oxide as an etch stop wherein any misalignment between said contact holes in said gate oxide and said photoresist mask will cause the formation of buried contact trenches in said buried contact regions; forming second test electrodes in said layer of first conductor material using said photoresist mask, dry anisotropic etching of said conductor material, and said layer of gate oxide as an etch stop wherein said second test electrodes are directly over said test holes in said layer of gate oxide and any misalignment between said test holes in said gate oxide and said photoresist mask will cause the formation of trenches in said first test electrodes; and measuring the resistance of said first test electrodes connected in series, thereby measuring the extent of said trenches in said first test electrodes and therefor also measuring the extent of said buried contact trenches.

Claim 2

A method of monitoring buried contact trench formation, comprising: providing a silicon integrated circuit wafer having chip regions with edges, test site regions, and a plurality of buried contact regions formed of active regions in said chip regions of said wafer; forming a first number of parallel first test electrodes on said integrated circuit wafer in each of said test site regions, wherein said parallel first test electrodes are formed by field isolation of active regions in said test site regions and are connected in series; forming a layer of gate oxide on said integrated circuit wafer, wherein said layer of gate oxide covers said chip regions and said test site regions; forming contact holes in said layer of gate oxide directly over each of said buried contact regions; forming a second number of test holes in said layer of gate oxide directly over each of said first test electrodes, wherein said test holes have the same size and shape as said contact holes and are formed at the same time said contact holes are formed; forming buried contacts through said contact holes in said buried contact regions; forming a layer of first conductor material on said layer of gate oxide after etching said contact holes and said test holes in said layer of gate oxide; forming a photoresist mask on said layer of first conductor material; forming contact electrodes and gate electrodes in said layer of first conductor material using said photoresist mask, dry anisotropic etching of said conductor material, and said layer of gate oxide as an etch stop wherein any misalignment between said contact holes in said gate oxide and said photoresist mask will cause the formation of buried contact trenches in said buried contact regions; forming second test electrodes in said layer of first conductor material using said photoresist mask, dry anisotropic etching of said conductor material, and said layer of gate oxide as an etch stop wherein said second test electrodes are directly over said test holes in said layer of gate oxide and any misalignment between said test holes in said gate oxide and said photoresist mask will cause the formation of trenches in said first test electrodes; and measuring the resistance of said first test electrodes connected in series, thereby measuring the extent of said trenches in said first test electrodes and therefor also measuring the extent of said buried contact trenches.