MMIC power amplifier with diagonal circuitry

Claim 2

A microwave power amplifier comprising: a first plurality of FETs arranged on an MMIC die in a first row, the first row being diagonal with respect to gate fingers of the FETs of the first plurality, said FETs of said first plurality being in an electrically parallel configuration; a second plurality of FETs arranged on the MMIC die in a second row, the second row being diagonal with respect to gate fingers of the FETs of the second plurality, said FETs of said second plurality being in an electrically parallel configuration; signal splitter circuitry for providing substantially in-phase signals to each FET of the first and second pluralities; and combiner circuitry for in-phase combining outputs of each of said FETs to provide an output signal.

Claim 3

A microwave power amplifier comprising: a first plurality of FETs arranged on an MMIC die in a first diagonal row, said FETs of said first plurality being in an electrically parallel configuration; a second plurality of FETs arranged on the MMIC die in a second diagonal row, said FETs of said second plurality being in an electrically parallel configuration; signal splitter circuitry for providing substantially in-phase signals to each FET of the first and second pluralities; and combiner circuitry for in-phase combining outputs of each of said FETs to provide an output signal, wherein said FETs of the first plurality overlap with adjacent FETs of the first plurality in a Y-dimension of the MMIC die, and said FETs of the first plurality do not overlap with adjacent FETs of the first plurality in a X-dimension of the MMIC die.

Claim 4

A microwave power amplifier comprising: a first plurality of FETs arranged on an MMIC die in a first diagonal row, said FETs of said first plurality being in an electrically parallel configuration; a second plurality of FETs arranged on the MMIC die in a second diagonal row, said FETs of said second plurality being in an electrically parallel configuration; signal splitter circuitry for providing substantially in-phase signals to each FET of the first and second pluralities; and combiner circuitry for in-phase combining outputs of each of said FETs to provide an output signal, wherein said FETs of the first plurality overlap with adjacent FETs of the first plurality in a Y-dimension of the MMIC die, and said FETs of the first plurality do not overlap with adjacent FETs of the first plurality in a X-dimension of the MMIC die.

Claim 5

The power amplifier as claimed in claim 2 wherein each FET of the first and second pluralities having gate fingers in parallel with gate fingers of the other FETs of the plurality.

Claim 6

A microwave power amplifier comprising: a first plurality of FETs arranged on an MMIC die in a first diagonal row, said FETs of said first plurality being in an electrically parallel configuration; a second plurality of FETs arranged on the MMIC die in a second diagonal row, said FETs of said second plurality being in an electrically parallel configuration; signal splitter circuitry for providing substantially in-phase signals to each FET of the first and second pluralities; combiner circuitry for in-phase combining outputs of each of said FETs to provide an output signal, a third plurality of FETs arranged on the MMIC die in a third diagonal row, said FETs of said third plurality being in an electrically parallel configuration; a fourth plurality of FETs arranged on the MMIC die in a fourth diagonal row, said FETs of said fourth plurality being in an electrically parallel configuration; wherein the third plurality of FETs provides first in-phase signals to said first plurality and the fourth plurality of FETs provides second in-phase signals to the second plurality; said first and second in-phase signals being in-phase with each other.

Claim 7

A microwave power amplifier comprising: a first plurality of FETs arranged on an MMIC die in a first diagonal row, said FETs of said first plurality being in an electrically parallel configuration; a second plurality of FETs arranged on the MMIC die in a second diagonal row, said FETs of said second plurality being in an electrically parallel configuration; signal splitter circuitry for providing substantially in-phase signals to each FET of the first and second pluralities; combiner circuitry for in-phase combining outputs of each of said FETs to provide an output signal, a third plurality of FETs arranged on the MMIC die in a third diagonal row, said FETs of said third plurality being in an electrically parallel configuration; a fourth plurality of FETs arranged on the MMIC die in a fourth diagonal row, said FETs of said fourth plurality being in an electrically parallel configuration; wherein the third plurality of FETs provides first in-phase signals to said first plurality and the fourth plurality of FETs provides second in-phase signals to the second plurality; said first and second in-phase signals being in-phase with each other.

Claim 8

The power amplifier as claimed in claim 4 wherein each FET of the third and fourth pluralities having their gate fingers in parallel with gate fingers of the other FETs of the third and fourth pluralities.

Claim 9

The power amplifier as claimed in claim 4 wherein the first and third diagonal rows are arranged on the MMIC die substantially in parallel with each other, and wherein the second and fourth diagonal rows are arranged on the MMIC die substantially in parallel with each other.

Claim 10

The power amplifier as claimed in claim 4 further comprising: a fifth plurality of FETs arranged on the MMIC die in a fifth diagonal row, said FETs of said fifth plurality being in an electrically parallel configuration; a sixth plurality of FETs arranged on the MMIC die in a sixth diagonal row, said FETs of said sixth plurality being in an electrically parallel configuration; wherein the fifth plurality of FETs provides third in-phase signals to said third plurality and the sixth plurality of FETs provides fourth in-phase signals to the fourth plurality; said third and fourth in-phase signals being substantially in-phase with each other.

Claim 11

The power amplifier as claimed in claim 7 wherein each FET of the fifth and sixth pluralities having their gate fingers in parallel with gate fingers of the other FETs of the fifth and sixth pluralities.

Claim 12

A microwave power amplifier comprising: a first plurality of FETs arranged on an MMIC die in a first diagonal row, said FETs of said first plurality being in an electrically parallel configuration; a second plurality of FETs arranged on the MMIC die in a second diagonal row, said FETs of said second plurality being in an electrically parallel configuration; signal splitter circuitry for providing substantially in-phase signals to each FET of the first and second pluralities; and combiner circuitry for in-phase combining outputs of each of said FETs to provide an output signal, wherein each FET of the first plurality has an width and a length dimension associated therewith, the width and length dimensions being planar with the MMIC die, wherein FETs of the first plurality are staggered along the first diagonal row, the first diagonal row having an X-dimension and a Y-dimension, the length dimension of said FETs of the first plurality being in the Y-dimension, the widths of the FETs of the first plurality being in the X-dimension.

Claim 13

A microwave power amplifier comprising: a first plurality of FETs arranged on an MMIC die in a first diagonal row, said FETs of said first plurality being in an electrically parallel configuration; a second plurality of FETs arranged on the MMIC die in a second diagonal row, said FETs of said second plurality being in an electrically parallel configuration; signal splitter circuitry for providing substantially in-phase signals to each FET of the first and second pluralities; and combiner circuitry for in-phase combining outputs of each of said FETs to provide an output signal, wherein each FET of the first plurality has an width and a length dimension associated therewith, the width and length dimensions being planar with the MMIC die, wherein FETs of the first plurality are staggered along the first diagonal row, the first diagonal row having an X-dimension and a Y-dimension, the length dimension of said FETs of the first plurality being in the Y-dimension, the widths of the FETs of the first plurality being in the X-dimension.

Claim 14

The power amplifier as claimed in claim 9 wherein the sum of lengths of all FETs of the first plurality is greater than a total length of said first diagonal row in the Y-dimension; and wherein the sum of widths of all FETs of the first plurality is less than a total width of said first diagonal row in the X-dimension.

Claim 15

The power amplifier as claimed in claim 10 wherein said FETs of the first plurality overlap with adjacent FETs of the first plurality in the Y-dimension, and said FETs of the first plurality do not overlap with adjacent FETs of the first plurality in the X-dimension.

Claim 16

The power amplifier as claimed in claim 11 wherein the first and second pluralities of FETs, the signal splitter circuitry, and the combiner circuitry are fabricated on a single MMIC die.

Claim 17

A MMIC power amplifier comprising: an MMIC substrate; and a plurality of FETs arranged on the MMIC substrate in first and second diagonal rows, said FETs being in an electrically parallel configuration, wherein each FET of the plurality has an width and a length dimension associated therewith, the width and length dimensions being planar with the MMIC substrate, the FETs being staggered along the first and second diagonal rows, the diagonal rows having an X-dimension and a Y-dimension associated therewith, the length dimension of said FETs being in the Y-dimension, the width dimension of the FETs being in the X-dimension, wherein said FETs along the first diagonal overlap with adjacent FETs in the Y-dimension, and said FETs along the second diagonal overlap with adjacent FETs in the Y-dimension.

Claim 18

A MMIC power amplifier comprising: an MMIC substrate; and a plurality of FETs arranged on the MMIC substrate in first and second diagonal rows, said FETs being in an electrically parallel configuration, wherein each FET of the plurality has an width and a length dimension associated therewith, the width and length dimensions being planar with the MMIC substrate, the FETs being staggered along the first and second diagonal rows, the diagonal rows having an X-dimension and a Y-dimension associated therewith, the length dimension of said FETs being in the Y-dimension, the width dimension of the FETs being in the X-dimension, wherein said FETs along the first diagonal overlap with adjacent FETs in the Y-dimension, and said FETs along the second diagonal overlap with adjacent FETs in the Y-dimension.

Claim 19

The MMIC power amplifier as claimed in claim 13 further comprising: signal splitter circuitry for providing substantially in-phase signals to each FET of the plurality; and combiner circuitry for in-phase combining outputs of each of said FETs to provide an output signal.

Claim 20

A microwave power amplifier comprising: a first plurality of FETs arranged on an MMIC die in a first diagonal row, said FETs of said first plurality being in an electrically parallel configuration; a second plurality of FETs arranged on the MMIC die in a second diagonal row, said FETs of said second plurality being in an electrically parallel configuration, wherein said FETs of the first plurality overlap with adjacent FETs of the first plurality in a Y-dimension of the MMIC die, and said FETs of the first plurality do not overlap with adjacent FETs of the first plurality in a X-dimension of the MMIC die, and wherein each FET of the first and second pluralities having gate fingers in parallel with gate fingers of the other FETs of the plurality; a third plurality of FETs arranged on the MMIC die in a third diagonal row, said FETs of said third plurality being in an electrically parallel configuration; a fourth plurality of FETs arranged on the MMIC die in a fourth diagonal row, said FETs of said fourth plurality being in an electrically parallel configuration, wherein the third plurality of FETs provides first in-phase signals to said first plurality and the fourth plurality of FETs provides second in-phase signals to the second plurality; said first and second in-phase signals being in-phase with each other, wherein each FET of the third and fourth pluralities having their gate fingers in parallel with gate fingers of the other FETs of the third and fourth pluralities; a fifth plurality of FETs arranged on the MMIC die in a fifth diagonal row, said FETs of said fifth plurality being in an electrically parallel configuration; a sixth plurality of FETs arranged on the MMIC die in a sixth diagonal row, said FETs of said sixth plurality being in an electrically parallel configuration, wherein the fifth plurality of FETs provides third in-phase signals to said third plurality and the sixth plurality of FETs provides fourth in-phase signals to the fourth plurality; said third and fourth in-phase signals being substantially in-phase with each other; signal splitter circuitry for providing substantially in-phase signals to each FET of the fifth and sixth pluralities; and combiner circuitry for in-phase combining outputs of each of said FETs of the first and second pluralities to provide an output signal.

Claim 21

A microwave power amplifier comprising: a first plurality of FETs arranged on an MMIC die in a first diagonal row, said FETs of said first plurality being in an electrically parallel configuration; a second plurality of FETs arranged on the MMIC die in a second diagonal row, said FETs of said second plurality being in an electrically parallel configuration, wherein said FETs of the first plurality overlap with adjacent FETs of the first plurality in a Y-dimension of the MMIC die, and said FETs of the first plurality do not overlap with adjacent FETs of the first plurality in a X-dimension of the MMIC die, and wherein each FET of the first and second pluralities having gate fingers in parallel with gate fingers of the other FETs of the plurality; a third plurality of FETs arranged on the MMIC die in a third diagonal row, said FETs of said third plurality being in an electrically parallel configuration; a fourth plurality of FETs arranged on the MMIC die in a fourth diagonal row, said FETs of said fourth plurality being in an electrically parallel configuration, wherein the third plurality of FETs provides first in-phase signals to said first plurality and the fourth plurality of FETs provides second in-phase signals to the second plurality; said first and second in-phase signals being in-phase with each other, wherein each FET of the third and fourth pluralities having their gate fingers in parallel with gate fingers of the other FETs of the third and fourth pluralities; a fifth plurality of FETs arranged on the MMIC die in a fifth diagonal row, said FETs of said fifth plurality being in an electrically parallel configuration; a sixth plurality of FETs arranged on the MMIC die in a sixth diagonal row, said FETs of said sixth plurality being in an electrically parallel configuration, wherein the fifth plurality of FETs provides third in-phase signals to said third plurality and the sixth plurality of FETs provides fourth in-phase signals to the fourth plurality; said third and fourth in-phase signals being substantially in-phase with each other; signal splitter circuitry for providing substantially in-phase signals to each FET of the fifth and sixth pluralities; and combiner circuitry for in-phase combining outputs of each of said FETs of the first and second pluralities to provide an output signal.

Claim 22

A microwave power anplifier comprising: a plurality of FETs arranged on an MTIC die in a first diagonal row, said FETs of said first plurality being in an electrically parallel configuration; signal splitter circuitry for providing substantially in-phase signals to each FET of the first purality; and combiner circuitry for in-phase combining outputs of each of said FETs to provide an output signal, wherein each FETs overlap with an adjacent FET of the plurality in a Y-dimension of the MMIC die, and each FET does not overlap with adjacent FETs of the plurality in a X-dimension of the MMIC die.

Claim 23

A microwave power anplifier comprising: a plurality of FETs arranged on an MTIC die in a first diagonal row, said FETs of said first plurality being in an electrically parallel configuration; signal splitter circuitry for providing substantially in-phase signals to each FET of the first purality; and combiner circuitry for in-phase combining outputs of each of said FETs to provide an output signal, wherein each FETs overlap with an adjacent FET of the plurality in a Y-dimension of the MMIC die, and each FET does not overlap with adjacent FETs of the plurality in a X-dimension of the MMIC die.