US5952846A
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Method for reducing switching noise in a programmable logic device
Assignee: Xilinx Inc
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Filing: 1997-08-08
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Granted: 1999-09-14
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Expires: 2017-08-08
Abstract
Abstract A method for programming PLDs in which feedback signals are alternately programmed to produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by multiple concurrent switching events. The method is applied to CPLDs having interconnect matrices including input lines and output lines connected by programmable connection circuits, and having macrocells connected at their output to one of the input lines via first selective inversion circuits, and connected at their input to the output lines via second selective inversion circuits. The method includes selecting a first macrocell generating a feedback signal which is routed to a second macrocell, generating a random command to either invert or not-invert the feedback signal, and, if the generated random command is to invert the feedback signal, programming the associated first selective inversion circuit to invert the feedback signal as it enters the interconnect matrix, and programming the associated second selective signal inversion circuit to re-invert the inverted feedback signal transmitted from the interconnect matrix to the second macrocell.
Inventors
- 👤 Joshua M. Silver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17764; H03K19/17736; H03K19/1778
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
159 words
A method for reducing switching noise in an interconnect matrix of a programmable logic device (PLD), the interconnect matrix including a plurality of input lines and a plurality of output lines, each input line being connectable to each output line by a programmable connection circuit, the PLD also including a plurality of macrocells, each macrocell having an output programmably connectable to one of the input lines, and an input programmably connectable to the output lines, the method comprising the steps of: selecting a first macrocell generating a feedback signal which is routed to the input of a second macrocell via a first input line and a first output line of the interconnect matrix; generating a command to either invert or not-invert the feedback signal; and if the command is to invert the feedback signal: inverting the feedback signal transmitted on the first input line; and re-inverting the inverted feedback signal transmitted from the interconnect matrix to the second macrocell.
Claim 2
Independent Claim
159 words
A method for reducing switching noise in an interconnect matrix of a programmable logic device (PLD), the interconnect matrix including a plurality of input lines and a plurality of output lines, each input line being connectable to each output line by a programmable connection circuit, the PLD also including a plurality of macrocells, each macrocell having an output programmably connectable to one of the input lines, and an input programmably connectable to the output lines, the method comprising the steps of: selecting a first macrocell generating a feedback signal which is routed to the input of a second macrocell via a first input line and a first output line of the interconnect matrix; generating a command to either invert or not-invert the feedback signal; and if the command is to invert the feedback signal: inverting the feedback signal transmitted on the first input line; and re-inverting the inverted feedback signal transmitted from the interconnect matrix to the second macrocell.
Claim 3
Dependent Claim
19 words
The method according to claim 1, wherein the step of generating a command comprises utilizing a random number generator.
Claim 4
Dependent Claim
26 words
The method according to claim 1, wherein the step of generating a command comprises utilizing a toggle circuit which alternates sequentially-generated commands between invert and not-invert.
Claim 5
Dependent Claim
34 words
The method according to claim 1, wherein the steps of inverting-and re-inverting are only performed if the feedback signal output from the first macrocell is not utilized to provide an interconnect matrix ANDing function.
Claim 6
Independent Claim
219 words
A method for reducing coupling noise in an interconnect matrix of a programmable logic device (PLD), the interconnect matrix including a plurality of input lines and a plurality of output lines, each input line being connected to each output line by a programmable connection circuit, the PLD also including a plurality of macrocells, each macrocell having an output programmably connectable to one of the input lines via an associated first selectively programmable signal inversion circuit, and an input programmably connectable to the output lines via an associated second selectively programmable signal inversion circuits, the method comprising the steps of: placing and routing a logic function such that portions of the logic function are implemented by some of the macrocells; selecting a first macrocell generating a feedback signal which is routed to the input of a second macrocell via a first input line and a first output line of the interconnect matrix; generating a command to either invert or not-invert the feedback signal; and if the generated random command is to invert the feedback signal: programming the associated first selectively programmable signal inversion circuit to invert the feedback signal transmitted on the first input line, and programming the associated second selectively programmable signal inversion circuit to re-invert the inverted feedback signal transmitted from the interconnect matrix to the second macrocell.
Claim 7
Independent Claim
219 words
A method for reducing coupling noise in an interconnect matrix of a programmable logic device (PLD), the interconnect matrix including a plurality of input lines and a plurality of output lines, each input line being connected to each output line by a programmable connection circuit, the PLD also including a plurality of macrocells, each macrocell having an output programmably connectable to one of the input lines via an associated first selectively programmable signal inversion circuit, and an input programmably connectable to the output lines via an associated second selectively programmable signal inversion circuits, the method comprising the steps of: placing and routing a logic function such that portions of the logic function are implemented by some of the macrocells; selecting a first macrocell generating a feedback signal which is routed to the input of a second macrocell via a first input line and a first output line of the interconnect matrix; generating a command to either invert or not-invert the feedback signal; and if the generated random command is to invert the feedback signal: programming the associated first selectively programmable signal inversion circuit to invert the feedback signal transmitted on the first input line, and programming the associated second selectively programmable signal inversion circuit to re-invert the inverted feedback signal transmitted from the interconnect matrix to the second macrocell.
Claim 8
Dependent Claim
19 words
The method according to claim 5, wherein the step of generating a command comprises utilizing a random number generator.
Claim 9
Dependent Claim
26 words
The method according to claim 5, wherein the step of generating a command comprises utilizing a toggle circuit which alternates sequentially-generated commands between invert and not-invert.
Claim 10
Dependent Claim
104 words
The method according to claim 5, wherein the associated first selectively programmable signal inversion circuit comprises a multiplexer having a first input connected to the output of the first macrocell, a second input connected to the output of the first macrocell via an inverter, and an output connected to the first input line of the interconnect matrix; wherein the step of programming the associated first selectively programmable signal inversion circuit comprises setting a memory cell associated with the multiplexer such that the output of the macrocell is connected to the first input line of the interconnect matrix through the second input and the inverter.
Claim 11
Dependent Claim
132 words
The method according to claim 5, wherein the associated second selectively programmable signal inversion circuit comprises: a buffer having an input connected to the output line of the interconnect matrix, a first output for transmitting the inverted feedback signal, and a second output for transmitting the re-inverted feedback signal, and a product-term line programmably connected to the first output via a first programmable connection, and to the second output of the buffer via a second programmable connection, the product term line being connected to the input of the macrocell; wherein the step of programming the associated second selectively programmable signal inversion circuit comprises programming the first programmable connection to disconnect the product-term line from the first output, and programming the second programmable connection to connect the product-term line to the second output.
Claim 12
Dependent Claim
51 words
The method according to claim 5, wherein the steps of programming the associated first selectively programmable signal inversion circuit and programming the associated second selectively programmable signal inversion circuit are only performed if the feedback signal output from the first macrocell is not utilized to provide an interconnect matrix ANDing function.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |