US5949689A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Path dependent power modeling
Assignee: Synopsys Inc
•
Filing: 1996-10-29
•
Granted: 1999-09-07
•
Expires: 2016-10-29
Abstract
Abstract A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell "library" within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition. Specifically, library designers are allowed to specify multiple internal power tables for each output with different "related -- pins" fields. To take advantage of the path dependent power modeling, library designers can specify multiple power tables in the library cell with different sets of related -- pins. Path dependent power modeling is important for those cells for which the path of the toggle makes the cell consume more or less power than the otherwise recorded "average" power rating used in conventional libraries. One example is the set/reset (SR) flip-flop.
Inventors
- 👤 Janet Olson
- 👤 James Sproch
- 👤 Yueqin Danny Lin
- 👤 Ivailo Nedelchev
- 👤 Ashutosh S. Mauskar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:53
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F2119/00; G06F2119/06
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
239 words
In a computer controlled power estimation system, a computer implemented method for providing a power consumption model for a physical circuit of an integrated circuit device, said method comprising the steps of: a) identifying a set of signal pins for a library cell representative of said physical circuit and storing said set of signal pins into a computer readable memory; b) designating at least one output signal pin of said library cell and storing a signal pin designation thereof into said power consumption model of said library cell within said computer readable memory; c) associated with said designated output signal pin, defining a first set of signal pins, wherein a transition on one signal pin of said first set causes said designated output signal pin to transition and wherein said first set contains more than one signal pins; d) associated with said designated output signal pin, defining a first power consumption function representative of power consumed by said physical circuit when a transition on one signal pin of said first set that causes said designated output signal pin to transition, said first power consumption function also representative of power consumed by said physical circuit when a transition on another signal pin of said first set causes said designated output signal pin to transition; and e) storing said first power consumption function and said first set into said power consumption model for said library cell of said computer readable memory.
Claim 2
Dependent Claim
239 words
In a computer controlled power estimation system, a computer implemented method for providing a power consumption model for a physical circuit of an integrated circuit device, said method comprising the steps of: a) identifying a set of signal pins for a library cell representative of said physical circuit and storing said set of signal pins into a computer readable memory; b) designating at least one output signal pin of said library cell and storing a signal pin designation thereof into said power consumption model of said library cell within said computer readable memory; c) associated with said designated output signal pin, defining a first set of signal pins, wherein a transition on one signal pin of said first set causes said designated output signal pin to transition and wherein said first set contains more than one signal pins; d) associated with said designated output signal pin, defining a first power consumption function representative of power consumed by said physical circuit when a transition on one signal pin of said first set that causes said designated output signal pin to transition, said first power consumption function also representative of power consumed by said physical circuit when a transition on another signal pin of said first set causes said designated output signal pin to transition; and e) storing said first power consumption function and said first set into said power consumption model for said library cell of said computer readable memory.
Claim 3
Dependent Claim
76 words
A method as described in claim 1 wherein said step d) comprises the steps of: defining a first power lookup table containing first reference index values; and defining a first set of reference power values associated with said first reference index values, said first set of reference power values representing said power consumed by said physical circuit when a transition on one signal pin of said first set causes said designated output signal pin to transition.
Claim 4
Dependent Claim
56 words
A method as described in claim 2 wherein said first power lookup table is a three dimensional lookup table having three indices comprising: a first output load capacitance index for said designated output pin; a second output load capacitance index for a second output pin of said library cell; and an input signal transition time index.
Claim 5
Dependent Claim
19 words
A method as described in claim 3 wherein said designated output pin and said second output pin switch contemporaneously.
Claim 6
Dependent Claim
124 words
A method as described in claim 1 further comprising the steps of: f) associated with said designated output signal pin, defining a second set of signal pins, wherein a transition on one signal pin of said second set causes said designated output signal pin to transition and wherein said second set contains one or more signal pins; g) associated with said designated output signal pin, defining a second power consumption function representative of power consumed by said physical circuit when a transition on one signal pin of said second set causes said designated output signal pin to transition; and h) storing said second power consumption function and said second set into said power consumption model for said library cell of said computer readable memory.
Claim 7
Dependent Claim
76 words
A method as described in claim 5 wherein said step g) comprises the steps of: defining a second power lookup table containing second reference index values; and defining a second set of reference power values associated with said second reference index values, said second set of reference power values representing said power consumed by said physical circuit when a transition on one signal pin of said second set causes said designated output signal pin to transition.
Claim 8
Dependent Claim
168 words
A method as described in claim 5 further comprising the steps of: simulating an integrated circuit design including said library cell representation of said physical circuit; monitoring said step of simulating for occurrences of transitions on said first set and said second set that cause said designated output signal pin of said library cell to transition; estimating power consumed by said library cell representation of said physical circuit using said power consumption model, said step of estimating further comprising the steps of: estimating power consumed by said library cell based on said first power consumption function provided a transition on a pin of said first set causes said designated output signal pin to transition; and estimating power consumed by said library cell based on said second power consumption function provided a transition on a pin of said second set causes said designated output signal pin to transition; and summing said above power estimations of said library cell over an interval during which said step of simulating is performed.
Claim 9
Dependent Claim
276 words
In a computer controlled power estimation system, a computer implemented method for providing a power consumption model for a physical circuit of an integrated circuit device, said method comprising the steps of: a) identifying a set of signal pins for a library cell representative of said physical circuit and storing said set of signal pins into a computer readable memory; b) designating at least one output signal pin of said library cell and storing a signal pin designation thereof into said power consumption model of said library cell within said computer readable memory; c) associated with said designated output signal pin, defining a first set of signal pins wherein said first set contains one or more signal pins; d) associated with said designated output signal pin, defining a first power consumption function representative of power consumed by said physical circuit when a transition on one signal pin of said first set causes said designated output signal pin to transition; e) storing said first power consumption function and said first set into said power consumption model for said library cell of said computer readable memory; f) associated with said designated output signal pin, defining a second set of signal pins wherein said second set contains one or more signal pins; g) associated with said designated output signal pin, defining a second power consumption function representative of power consumed by said physical circuit when a transition on one signal pin of said second set causes said designated output signal pin to transition; and h) storing said second power consumption function and said second set into said power consumption model for said library cell of said computer readable memory.
Claim 10
Dependent Claim
276 words
In a computer controlled power estimation system, a computer implemented method for providing a power consumption model for a physical circuit of an integrated circuit device, said method comprising the steps of: a) identifying a set of signal pins for a library cell representative of said physical circuit and storing said set of signal pins into a computer readable memory; b) designating at least one output signal pin of said library cell and storing a signal pin designation thereof into said power consumption model of said library cell within said computer readable memory; c) associated with said designated output signal pin, defining a first set of signal pins wherein said first set contains one or more signal pins; d) associated with said designated output signal pin, defining a first power consumption function representative of power consumed by said physical circuit when a transition on one signal pin of said first set causes said designated output signal pin to transition; e) storing said first power consumption function and said first set into said power consumption model for said library cell of said computer readable memory; f) associated with said designated output signal pin, defining a second set of signal pins wherein said second set contains one or more signal pins; g) associated with said designated output signal pin, defining a second power consumption function representative of power consumed by said physical circuit when a transition on one signal pin of said second set causes said designated output signal pin to transition; and h) storing said second power consumption function and said second set into said power consumption model for said library cell of said computer readable memory.
Claim 11
Dependent Claim
63 words
A method as described in claim 8 wherein said first power consumption function and said second power consumption function each comprises a three dimensional lookup table having three indices comprising: a first output load capacitance index for said designated output pin; a second output load capacitance index for a second output pin of said library cell; and an input signal transition time index.
Claim 12
Dependent Claim
19 words
A method as described in claim 9 wherein said designated output pin and said second output pin switch contemporaneously.
Claim 13
Dependent Claim
76 words
A method as described in claim 8 wherein said step d) comprises the steps of: defining a first power lookup table containing first reference index values; and defining a first set of reference power values associated with said first reference index values, said first set of reference power values representing said power consumed by said physical circuit when a transition on one signal pin of said first set causes said designated output signal pin to transition.
Claim 14
Dependent Claim
76 words
A method as described in claim 11 wherein said step g) comprises the steps of: defining a second power lookup table containing second reference index values; and defining a second set of reference power values associated with said second reference index values, said second set of reference power values representing said power consumed by said physical circuit when a transition on one signal pin of said second set causes said designated output signal pin to transition.
Claim 15
Dependent Claim
168 words
A method as described in claim 8 further comprising the steps of: simulating an integrated circuit design including said library cell representation of said physical circuit; monitoring said step of simulating for occurrences of transitions on said first set and said second set that cause said designated output signal pin of said library cell to transition; estimating power consumed by said library cell representation of said physical circuit using said power consumption model, said step of estimating further comprising the steps of: estimating power consumed by said library cell based on said first power consumption function provided a transition on a pin of said first set causes said designated output signal pin to transition; and estimating power consumed by said library cell based on said second power consumption function provided a transition on a pin of said second set causes said designated output signal pin to transition; and summing said above power estimations of said library cell over an interval during which said step of simulating is performed.
Claim 16
Dependent Claim
167 words
A computer readable memory having stored therein a power consumption model used for estimating power consumed by a physical circuit of an integrated circuit device, said power model comprising: a designation for a set of pins for a library cell representative of said physical circuit; a designation of at least one designated output signal pin of said library cell; associated with said designated output signal pin, a definition of a first set of pins of said library cell wherein said first set of pins comprises more than one pins; and associated with said designated output signal pin, a definition of a first power consumption function representative of power consumed by said physical circuit when a transition on a pin of said first set of pins causes said designated output signal pin to transition, said first power consumption function also representative of power consumed by said physical circuit when a transition on another pin of said first set of pins causes said designated output signal pin to transition.
Claim 17
Dependent Claim
167 words
A computer readable memory having stored therein a power consumption model used for estimating power consumed by a physical circuit of an integrated circuit device, said power model comprising: a designation for a set of pins for a library cell representative of said physical circuit; a designation of at least one designated output signal pin of said library cell; associated with said designated output signal pin, a definition of a first set of pins of said library cell wherein said first set of pins comprises more than one pins; and associated with said designated output signal pin, a definition of a first power consumption function representative of power consumed by said physical circuit when a transition on a pin of said first set of pins causes said designated output signal pin to transition, said first power consumption function also representative of power consumed by said physical circuit when a transition on another pin of said first set of pins causes said designated output signal pin to transition.
Claim 18
Dependent Claim
90 words
A computer readable memory as described in claim 14 wherein said power consumption model further comprises: associated with said designated output signal pin, a definition of a second set of pins of said library cell wherein said second set of pins comprises one or more pins; and associated with said designated output signal pin, a definition of a second power consumption function representative of power consumed by said physical circuit when a transition on a pin of said second set of pins causes said designated output signal pin to transition.
Claim 19
Dependent Claim
65 words
A computer readable memory as described in claim 15 wherein said first power consumption function and said second power consumption function each comprises a three dimensional lookup table having three indices comprising: a first output load capacitance index for said designated output pin; a second output load capacitance index for a second output pin of said library cell; and an input signal transition time index.
Claim 20
Dependent Claim
21 words
A computer readable memory as described in claim 16 wherein said designated output pin and said second output pin switch contemporaneously.
Claim 21
Dependent Claim
84 words
A computer readable memory as described in claim 15 wherein said first power consumption function comprises: a representation of a first power lookup table, said first power lookup table containing first reference index values; and a first set of reference power values associated with said first reference index values, said first set of reference power values representing said power consumed by said physical circuit when a transition on a pin of said first set of pins causes said designated output signal pin to transition.
Claim 22
Dependent Claim
84 words
A computer readable memory as described in claim 18 wherein said second power consumption function comprises: a representation of a second power lookup table, said second power lookup table containing second reference index values; and a second set of reference power values associated with said second reference index values, said second set of reference power values representing said power consumed by said physical circuit when a transition on a pin of said second set of pins causes said designated output signal pin to transition.
Claim 23
Dependent Claim
192 words
A computer readable memory as described in claim 15 further comprising instruction code stored therein that when executed over a processor, causing a computer system to implement the following steps: a) simulating an integrated circuit design including said library cell representation of said physical circuit; b) monitoring said step of simulating for occurrences of transitions on said first set and said second set that cause said designated output signal pin of said library cell to transition; c) estimating power consumed by said library cell representation of said physical circuit using said power consumption model, said step of estimating further comprising the steps of: 1) estimating power consumed by said library cell based on said first power consumption function provided a transition on a pin of said first set causes said designated output signal pin to transition; and 2) estimating power consumed by said library cell based on said second power consumption function provided a transition on a pin of said second set causes said designated output signal pin to transition; and d) summing said above power estimations of said library cell over an interval during which said step of simulating is performed.
References Cited (Backward Citations)
US5050091A
Cited
US5267175A
Cited
US5530841A
Cited
US5473548A
Cited
US5535370A
Cited
US5673200A
Cited
US5602753A
Cited
US5682320A
Cited
US5696694A
Cited
US5625803A
Cited
US5692160A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-06 | 2003-03-08 | 2003-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-06 | 2007-03-08 | 2007-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-06 | 2011-03-08 | 2011-09-07 | $7700.00 | Window Closed / Lapsed |