Abstract A method of removing an etch-stop layer such as Si 3 N 4 from the vicinity of contact openings is described. A need for the removal of this material arises when the surface of the etch-stop layer is exposed during processing and the substrate is subjected to temperatures above 700° C. Because of the high intrinsic interfacial stress residing in the Si 3 N 4 , the thermal impact causes cracks in the layer which emanate from the corners of the contact openings and travel, with branching, over a considerable distance from the opening. These cracks are prone to moisture adsorption and contamination which can compromise the reliability and performance of contacts. In addition, where contact openings are formed through insulating layers having an intermediate etch-stop layer, protrusions of the etch-stop layer occur within the contact opening because of un-even etching. These protrusions shadow the flux of subsequently deposited barrier materials into the opening, thereby forming weak spots along the contact walls. Timely removal the etch-stop layer around the contact opening eliminates these protrusions.
A method for preventing the formation of cracks in an etch-stop layer next to contact openings during the formation of an SiO 2 /Si 3 N 4 /SiO 2 capacitor dielectric comprising: (a) providing a wafer having an etch-stop layer with an exposed planar surface next to contact openings and wherein said etch stop layer is does not extend into said contact openings; (b) depositing a photoresist layer in contact with said etch-stop layer; (c) patterning said photoresist layer to expose an area of said etch-stop layer next to said contact openings; (d) etching said area of etch-stop layer; and (e) after step (d), forming an SiO 2 /Si 3 N 4 /SiO 2 dielectric layer on said wafer whereby said wafer is subjected to a temperature of 700° C. or thereabout.
Claim 2
Independent Claim
132 words
A method for preventing the formation of cracks in an etch-stop layer next to contact openings during the formation of an SiO 2 /Si 3 N 4 /SiO 2 capacitor dielectric comprising: (a) providing a wafer having an etch-stop layer with an exposed planar surface next to contact openings and wherein said etch stop layer is does not extend into said contact openings; (b) depositing a photoresist layer in contact with said etch-stop layer; (c) patterning said photoresist layer to expose an area of said etch-stop layer next to said contact openings; (d) etching said area of etch-stop layer; and (e) after step (d), forming an SiO 2 /Si 3 N 4 /SiO 2 dielectric layer on said wafer whereby said wafer is subjected to a temperature of 700° C. or thereabout.
Claim 3
Dependent Claim
26 words
The method of claim 1 wherein said etch-stop layer is taken from the group consisting of Si 3 N 4 and Al 2 O 3 .
Claim 4
Dependent Claim
24 words
The method of claim 2 wherein said etch-stop layer is deposited by low-pressure-chemical-vapor-deposition at a temperature of between about 650° C. and 800° C.
Claim 5
Dependent Claim
11 words
The method of claim 2 wherein said etching is plasma etching.
Claim 6
Dependent Claim
17 words
The method of claim 1 wherein said etch-stop layer is between about 200 and 2,000 Angstroms thick.