US5942773A
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Field effect transistor with reduced delay variation
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1996-12-23
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Granted: 1999-08-24
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Expires: 2016-12-23
Abstract
Abstract A field effect transistor with a reduced delay variation is provided in a compound semiconductor layer with a channel, a source, and a drain region of a first conduction type. A gate electrode, a source electrode, and a drain electrode are formed respectively on the regions mentioned above. Particularly the gate electrode formed on the channel is provided with a projecting part extended in a direction crossing the direction of opposition of the source and drain region and caused to protrude from the channel region. In the compound semiconductor layer, a well region of a second conduction type opposite to the first conduction type is formed so as to enclose the channel region, the source region, the drain region, and the projecting part of the gate electrode more deeply than in the channel, source, and drain regions. The delay variation is markedly reduced by the fact that the gate electrode including the projecting part is enclosed with the well region of the second conduction type.
Inventors
- 👤 Yoshiaki Kaneko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:03
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10P; H10P10/00; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
151 words
A field effect transistor, comprising: a compound semiconductor layer; a channel region of a first conduction type formed in said compound semiconductor layer; a source and a drain regions of said first conduction type formed in said compound semiconductor layer opposite each other across said channel region; a gate electrode formed on said channel region, extended in a direction crossing a source and drain region direction, and provided with a projecting part protruding from said channel region in a horizontal plane; a source and a drain electrodes electrically connected to said source and drain regions; and a well region of a second conduction type opposite to said first conduction type, formed in said compound semiconductor layer, adapted to enclose therewith said channel region, said source and drain regions, and the projecting part of said gate electrode, and formed in a depth greater than said channel and said source and drain regions.
Claim 2
Dependent Claim
151 words
A field effect transistor, comprising: a compound semiconductor layer; a channel region of a first conduction type formed in said compound semiconductor layer; a source and a drain regions of said first conduction type formed in said compound semiconductor layer opposite each other across said channel region; a gate electrode formed on said channel region, extended in a direction crossing a source and drain region direction, and provided with a projecting part protruding from said channel region in a horizontal plane; a source and a drain electrodes electrically connected to said source and drain regions; and a well region of a second conduction type opposite to said first conduction type, formed in said compound semiconductor layer, adapted to enclose therewith said channel region, said source and drain regions, and the projecting part of said gate electrode, and formed in a depth greater than said channel and said source and drain regions.
Claim 3
Dependent Claim
29 words
The field effect transistor according to claim 1, wherein said gate electrode is provided with a gate pad part having a width greater than that of said gate electrode.
Claim 4
Dependent Claim
22 words
The field effect transistor according to claim 2, wherein said well region is formed so as to enclose said gate pad part.
Claim 5
Dependent Claim
38 words
The field effect transistor according to claim 1, wherein said source and drain electrodes have parts projecting out of said source and drain regions and said well region is formed so as to enclose therewith said projecting parts.
Claim 6
Dependent Claim
44 words
The field effect transistor according to claim 4, wherein the distance between a boundary of said well region and said channel region, said source and drain regions, and a region of the projecting part of said gate electrode is not less than 0.3 μm.
Claim 7
Dependent Claim
24 words
The field effect transistor according to claim 5, wherein said distance is larger than the total of 0.3 μm plus a mask alignment margin.
Claim 8
Dependent Claim
29 words
The field effect transistor according to claim 1, wherein the projecting part of said gate electrode protrudes not less than 0.5 μm from the boundary of said channel region.
Claim 9
Dependent Claim
21 words
The field effect transistor according to claim 1, wherein said compound semiconductor layer is formed on a semi-insulating compound semiconductor substrate.
Claim 10
Dependent Claim
29 words
The field effect transistor according to claim 1, wherein said well region is of a p type and said channel, source, and drain regions are of an n type.
Claim 11
Dependent Claim
29 words
The field effect transistor according to claim 1, wherein said well region is of an n type and said channel, source, and drain regions are of a p type.
Claim 12
Dependent Claim
23 words
The field effect transistor according to claim 1, wherein said well region has connected thereto a potential-imparting electrode for imparting a prescribed potential.
Claim 13
Dependent Claim
37 words
The field effect transistor according to claim 11, wherein an area to which said potential-imparting electrode is connected has incorporated therein an impurity of said second conductivity type at a concentration higher than in said well region.
Claim 14
Dependent Claim
19 words
The field effect transistor according to claim 11, wherein said prescribed potential-imparting electrode is connected to a ground potential.
Claim 15
Dependent Claim
85 words
The field effect transistor according to claim 1, wherein said channel region has two LDD regions, one of said LDD regions being formed between said source electrode and said gate electrode, and another of said LDD regions being formed between said drain electrode and said gate electrode, said LDD regions have incorporated therein an impurity of said first conduction type having impurity concentration higher than that in the channel region directly below said gate electrode and lower than that in said source and drain regions.
Claim 16
Dependent Claim
40 words
The field effect transistor according to claim 1, wherein said well region is provided in the periphery thereof with an element separating region having the same conductivity type as said well region and a higher concentration than said well region.
Claim 17
Dependent Claim
168 words
A semiconductor integrated circuit device having integrated in a compound semiconductor layer thereof a plurality of field effect transistors each comprising: a) a channel region of a first conduction type formed in said compound semiconductor layer; b) a source and a drain regions of said first conduction type formed in said compound semiconductor layer opposite each other across said channel region; c) a gate electrode formed on said channel region, extended in a direction crossing a source and drain region direction, and provided with a projecting part protruding from said channel region in a horizontal plane; d) a source and a drain electrodes electrically connected to said source and drain regions; and e) a well region of a second conduction type opposite to said first conduction type, formed in said compound semiconductor layer, adapted to enclose therewith said channel region, said source and drain regions, and the projecting part of said gate electrode, and formed in a depth greater than said channel and said source and drain regions.
Claim 18
Dependent Claim
168 words
A semiconductor integrated circuit device having integrated in a compound semiconductor layer thereof a plurality of field effect transistors each comprising: a) a channel region of a first conduction type formed in said compound semiconductor layer; b) a source and a drain regions of said first conduction type formed in said compound semiconductor layer opposite each other across said channel region; c) a gate electrode formed on said channel region, extended in a direction crossing a source and drain region direction, and provided with a projecting part protruding from said channel region in a horizontal plane; d) a source and a drain electrodes electrically connected to said source and drain regions; and e) a well region of a second conduction type opposite to said first conduction type, formed in said compound semiconductor layer, adapted to enclose therewith said channel region, said source and drain regions, and the projecting part of said gate electrode, and formed in a depth greater than said channel and said source and drain regions.
Claim 19
Dependent Claim
38 words
The semiconductor integrated circuit device according to claim 16, wherein some transistors of said plurality of integrated field effect transistors form a common output circuit, said some transistors having well layers thereof interconnected within compound semiconductor layers thereof.
Claim 20
Dependent Claim
20 words
The semiconductor integrated circuit device according to claim 16, wherein said plurality of field effect transistors are connected in series.
Claim 21
Dependent Claim
28 words
The semiconductor integrated circuit device according to claim 18, wherein said plurality of series connected field effect transistors have the well regions thereof electrically separated from one another.
References Cited (Backward Citations)
JPS5856471A
Cited
JPS58123753A
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JPH03104239A
Cited
JPH0427153A
Cited
US5324969A
Cited
JPH0714989A
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