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US5937295A Expired / Lapsed US ⏱️ 0.0 years remaining

Nano-structure memory device

Assignee: GlobalFoundries Inc
•
Filing: 1997-10-07
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Granted: 1999-08-10
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Expires: 2017-10-07
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Abstract

Abstract A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control barrier layer, and a gate electrode. The nanocrystal which may be a quantum dot, stores one electron or hole or a discrete number of electrons or holes at room temperature to provide threshold voltage shifts in excess of the thermal voltage for each change in electron or hole stored. The invention utilizes Coulomb blockade in electrostatically coupling one or more stored electrons or holes to a channel while avoiding in-path Coulomb-blockade controlled conduction for sensing the stored charge.

Inventors

  • 👤 Wei Chen
  • 👤 Theoren Perlee Smith, III
  • 👤 Sandip Tiwari

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 05:23
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/688; B; B82; B82Y; B82Y10/00; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; H10D30/01; H10D30/021; H10D30/0411; H10D30/687; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/832; G11C2216/00; G11C2216/02; G11C2216/08; Y; Y10; Y10S; Y10S438/00; Y10S438/962

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 99 words
A method for forming a memory device comprising the steps of: selecting a substrate, forming a layer of semiconductor material on said substrate, forming a first layer of insulation having a thickness to form an injection insulator, forming a nanocrystal on said first layer of insulation, forming a second layer of insulation on said nanocrystal to function as a control insulator, forming a gate electrode layer on said second layer of insulation, and etching said first layer, nanocrystal, second layer and gate electrode layer to form a gate stack over a channel region of said layer of semiconductor material.
Claim 2
Independent Claim 99 words
A method for forming a memory device comprising the steps of: selecting a substrate, forming a layer of semiconductor material on said substrate, forming a first layer of insulation having a thickness to form an injection insulator, forming a nanocrystal on said first layer of insulation, forming a second layer of insulation on said nanocrystal to function as a control insulator, forming a gate electrode layer on said second layer of insulation, and etching said first layer, nanocrystal, second layer and gate electrode layer to form a gate stack over a channel region of said layer of semiconductor material.
Claim 3
Dependent Claim 32 words
The method of claim 1 wherein said step of forming a nanocrystal includes the step of forming a plurality of nanocrystals spaced apart from one another on said first layer of insulation.
Claim 4
Dependent Claim 44 words
The method of claim 2 wherein said step of forming a nanocrystal includes the step of forming a plurality of nanocrystals spaced apart from one another in an insulator material to form a three dimensional array of nanocrystals on said first layer of insulation.

References Cited (Backward Citations)

US5354707A Cited
US5670790A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-08-09 2003-02-08 2003-08-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-08-09 2007-02-08 2007-08-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-08-09 2011-02-08 2011-08-10 $7700.00 Window Closed / Lapsed

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