Apparatus for allowing data transfers with a memory having defective storage locations

Claim 2

In a computer storage medium containing data stored in a data structure for use by a computer, the data structure comprising: a first set of storage locations at each address of the computer storage medium in which one or more of the storage locations may be defective, the storage locations in the first set having received respective bits of data and stored at least some of the bits of data in respective, non-defective storage locations; a second set of storage locations at each address, the storage locations in the second set containing a record of defective storage locations in the first set at the corresponding address in the storage medium; and a set of substitute storage locations at each address, the number of storage locations in the set of substitute storage locations being less than the number of storage locations in the first set at the corresponding address, the substitute storage locations storing the respective bits of data received by any defective storage locations in the first set of storage locations at the corresponding address in the storage medium.

Claim 3

The data structure of claim 1 wherein the record of defective storage locations at each address in the storage medium is stored at a second set of storage locations at the address, the storage locations in the second set being different from the storage locations in the first set of storage locations and the substitute storage locations.

Claim 4

The data structure of claim 2 wherein the storage medium includes at each address 64 storage locations in the first set of storage locations, 4 substitute storage locations adapted to substitute for 4 storage locations in the first set of storage locations, and 4 storage locations in the second set of storage locations adapted to identify each of 16 sets of 4 contiguous storage locations in the first set for which the substitute storage locations are to be used.

Claim 5

The data structure of claim 1 wherein the storage medium comprises a dynamic random access memory.

Claim 6

A memory correction system for allowing data to be written to and read from a memory device having a plurality of memory locations at each of a plurality of addresses in which one or more memory locations at each address may be defective, the memory locations at each address being divided into a first set of memory locations corresponding in number to at least the number of bits in the data to be stored in the memory device, and a second set of memory locations adapted to substitute for defective memory locations in the first set, the memory device further including a data bus having a plurality of bits coupled to respective memory locations of the memory device at each address; the memory correction system comprising: a storage device containing defect data identifying any defective storage locations in the first set of memory locations in the memory device for each address in the memory device; a data input path circuit coupling an external data bus to the data bus of the memory device, the data input path circuit comprising: a write multiplexer coupling each bit of the external data bus to a respective memory location in the first set of memory locations at each address when a first enable signal for the memory location is inactive, and coupling a bit of the external data bus to a respective memory location in the second set of memory locations at each address when a first enable signal for the memory location is active; and a write decoder coupled to the write multiplexer and to the storage device, the write decoder decoding the defect data to generate and apply an active first enable signal to the write multiplexer for each memory location in the first set that is identified by the defect data as being defective and to generate and apply an inactive first enable signal to the write multiplexer for each remaining memory location in the first set; and a data output path circuit coupling the data bus of the memory device to the external data bus, the data output path circuit comprising: a read multiplexer coupling each memory location in the first set of memory locations at each address to a respective bit of the external data bus when a second enable signal for the memory location is inactive, and coupling a memory location in the second set of memory locations at each address to a bit of the external data bus when a second enable signal for the memory location is active; and a read decoder coupled to the read multiplexer and to the storage device, the read decoder decoding the defect data to generate and apply an active second enable signal to the read multiplexer for each memory location in the first set that is identified by the defect data as being defective and to generate and apply an inactive second enable signal to the read multiplexer for each remaining memory location in the first set.

Claim 7

A memory correction system for allowing data to be written to and read from a memory device having a plurality of memory locations at each of a plurality of addresses in which one or more memory locations at each address may be defective, the memory locations at each address being divided into a first set of memory locations corresponding in number to at least the number of bits in the data to be stored in the memory device, and a second set of memory locations adapted to substitute for defective memory locations in the first set, the memory device further including a data bus having a plurality of bits coupled to respective memory locations of the memory device at each address; the memory correction system comprising: a storage device containing defect data identifying any defective storage locations in the first set of memory locations in the memory device for each address in the memory device; a data input path circuit coupling an external data bus to the data bus of the memory device, the data input path circuit comprising: a write multiplexer coupling each bit of the external data bus to a respective memory location in the first set of memory locations at each address when a first enable signal for the memory location is inactive, and coupling a bit of the external data bus to a respective memory location in the second set of memory locations at each address when a first enable signal for the memory location is active; and a write decoder coupled to the write multiplexer and to the storage device, the write decoder decoding the defect data to generate and apply an active first enable signal to the write multiplexer for each memory location in the first set that is identified by the defect data as being defective and to generate and apply an inactive first enable signal to the write multiplexer for each remaining memory location in the first set; and a data output path circuit coupling the data bus of the memory device to the external data bus, the data output path circuit comprising: a read multiplexer coupling each memory location in the first set of memory locations at each address to a respective bit of the external data bus when a second enable signal for the memory location is inactive, and coupling a memory location in the second set of memory locations at each address to a bit of the external data bus when a second enable signal for the memory location is active; and a read decoder coupled to the read multiplexer and to the storage device, the read decoder decoding the defect data to generate and apply an active second enable signal to the read multiplexer for each memory location in the first set that is identified by the defect data as being defective and to generate and apply an inactive second enable signal to the read multiplexer for each remaining memory location in the first set.

Claim 8

The memory correction system of claim 5 wherein the storage device comprises a third set of memory locations at each address of the memory device, the third set of memory locations storing at each address the defect data identifying any defective storage locations in the first set of memory locations in the memory device at that address.

Claim 9

The memory correction system of claim 6 wherein the memory device includes at each address 64 memory locations in the first set of memory locations, 4 substitute memory locations in the second set adapted to substitute for 4 memory locations in the first set of memory locations, and 4 memory locations in the third set of memory locations adapted to identify each of 16 sets of 4 contiguous memory locations in the first set for which the substitute memory locations in the second set are to be used.

Claim 10

The memory correction system of claim 5 wherein the memory device comprises a dynamic random access memory.

Claim 11

The memory correction system of claim 5 wherein the memory device includes at each address 64 memory locations in the first set of memory locations, and 4 substitute memory locations in the second set adapted to substitute for 4 memory locations in the first set of memory locations.

Claim 12

The memory correction system of claim 5 wherein the storage device comprises a non-volatile memory containing the defect data.

Claim 13

The memory correction system of claim 10 wherein the non-volatile memory comprises a read only memory.

Claim 14

A computer system, comprising: an input device adapted to receive information from a user; an output device adapted to provide information to a user; a processor coupled to the input device and the output device, the processor being structured to process data according to programmed instructions; a memory device having a plurality of memory locations at each of a plurality of addresses, the memory locations at each address being divided into a first set of memory locations corresponding in number to at least the number of bits in the data to be stored in the memory device, and a second set of memory locations adapted to substitute for defective memory locations in the first set, the memory device further including a data bus having a plurality of bits coupled to respective memory locations of the memory device at each address; a memory controller coupling the data bus of the memory device to the processor, the memory device including a memory correction system for allowing data to be written to and read from the memory device even though one or more memory locations in the first set of memory addresses at each address may be defective, the memory correction system comprising: a storage device containing defect data identifying any defective storage locations in the first set of memory locations in the memory device for each address in the memory device; a data input path circuit coupling an external data bus to the data bus of the memory device, the data input path circuit comprising: a write multiplexer coupling each bit of the external data bus to a respective memory location in the first set of memory locations at each address when a first enable signal for the memory location is inactive, and coupling a bit of the external data bus to a respective memory location in the second set of memory locations at each address when a first enable signal for the memory location is active; and a write decoder coupled to the write multiplexer and to the storage device, the write decoder decoding the defect data to generate and apply an active first enable signal to the write multiplexer for each memory location in the first set that is identified by the defect data as being defective and to generate and apply an inactive first enable signal to the write multiplexer for each remaining memory location in the first set; and a data output path circuit coupling the data bus of the memory device to the external data bus, the data output path circuit comprising: a read multiplexer coupling each memory location in the first set of memory locations at each address to a respective bit of the external data bus when a second enable signal for the memory location is inactive, and coupling a memory location in the second set of memory locations at each address to a bit of the external data bus when a second enable signal for the memory location is active; and a read decoder coupled to the read multiplexer and to the storage device, the read decoder decoding the defect data to generate and apply an active second enable signal to the read multiplexer for each memory location in the first set that is identified by the defect data as being defective and to generate and apply an inactive second enable signal to the read multiplexer for each remaining memory location in the first set.

Claim 15

A computer system, comprising: an input device adapted to receive information from a user; an output device adapted to provide information to a user; a processor coupled to the input device and the output device, the processor being structured to process data according to programmed instructions; a memory device having a plurality of memory locations at each of a plurality of addresses, the memory locations at each address being divided into a first set of memory locations corresponding in number to at least the number of bits in the data to be stored in the memory device, and a second set of memory locations adapted to substitute for defective memory locations in the first set, the memory device further including a data bus having a plurality of bits coupled to respective memory locations of the memory device at each address; a memory controller coupling the data bus of the memory device to the processor, the memory device including a memory correction system for allowing data to be written to and read from the memory device even though one or more memory locations in the first set of memory addresses at each address may be defective, the memory correction system comprising: a storage device containing defect data identifying any defective storage locations in the first set of memory locations in the memory device for each address in the memory device; a data input path circuit coupling an external data bus to the data bus of the memory device, the data input path circuit comprising: a write multiplexer coupling each bit of the external data bus to a respective memory location in the first set of memory locations at each address when a first enable signal for the memory location is inactive, and coupling a bit of the external data bus to a respective memory location in the second set of memory locations at each address when a first enable signal for the memory location is active; and a write decoder coupled to the write multiplexer and to the storage device, the write decoder decoding the defect data to generate and apply an active first enable signal to the write multiplexer for each memory location in the first set that is identified by the defect data as being defective and to generate and apply an inactive first enable signal to the write multiplexer for each remaining memory location in the first set; and a data output path circuit coupling the data bus of the memory device to the external data bus, the data output path circuit comprising: a read multiplexer coupling each memory location in the first set of memory locations at each address to a respective bit of the external data bus when a second enable signal for the memory location is inactive, and coupling a memory location in the second set of memory locations at each address to a bit of the external data bus when a second enable signal for the memory location is active; and a read decoder coupled to the read multiplexer and to the storage device, the read decoder decoding the defect data to generate and apply an active second enable signal to the read multiplexer for each memory location in the first set that is identified by the defect data as being defective and to generate and apply an inactive second enable signal to the read multiplexer for each remaining memory location in the first set.

Claim 16

The computer system of claim 12 wherein the storage device comprises a third set of memory locations at each address of the memory device, the third set of memory locations storing at each address the defect data identifying any defective storage locations in the first set of memory locations in the memory device at that address.

Claim 17

The computer system of claim 13 wherein the memory device includes at each address 64 memory locations in the first set of memory locations, 4 substitute memory locations in the second set adapted to substitute for 4 memory locations in the first set of memory locations, and 4 memory locations in the third set of memory locations adapted to identify each of 16 sets of 4 contiguous memory locations in the first set for which the substitute memory locations in the second set are to be used.

Claim 18

The computer system of claim 12 wherein the storage device comprises a non-volatile memory containing the defect data.

Claim 19

The computer system of claim 15 wherein the non-volatile memory comprises a read only memory.

Claim 20

The computer system of claim 12 wherein the memory device comprises a dynamic random access memory.

Claim 21

The computer system of claim 12 wherein the memory device includes at each address 64 memory locations in the first set of memory locations, and 4 substitute memory locations in the second set adapted to substitute for 4 memory locations in the first set of memory locations.

Claim 22

A program storage device storing instructions that, when executed by a processor, perform a plurality of steps in connection with a memory, the steps comprising: maintaining a record of defective memory locations at each address of the memory; in response to receiving a first address directed to the memory, checking the record of defective memory locations to determine if there are any defective memory locations at the first address in the memory; if there are no defective memory locations at the first address, writing the data to corresponding memory locations in a first set of memory locations at the first address; and if there is at least one defective memory location at the first address, writing a subset of the data to respective substitute memory locations at the first address, the subset of data including the data that would be written to each defective memory location in the first set of memory locations at the first address, and writing the data not in the subset to corresponding memory locations in the first set of memory locations at the first address.

Claim 23

A program storage device storing instructions that, when executed by a processor, perform a plurality of steps in connection with a memory, the steps comprising: maintaining a record of defective memory locations at each address of the memory; in response to receiving a first address directed to the memory, checking the record of defective memory locations to determine if there are any defective memory locations at the first address in the memory; if there are no defective memory locations at the first address, writing the data to corresponding memory locations in a first set of memory locations at the first address; and if there is at least one defective memory location at the first address, writing a subset of the data to respective substitute memory locations at the first address, the subset of data including the data that would be written to each defective memory location in the first set of memory locations at the first address, and writing the data not in the subset to corresponding memory locations in the first set of memory locations at the first address.

Claim 24

The program storage device of claim 19 wherein the stored instructions further cause the processor to perform the step of storing the record of defective memory locations at each address in the memory at a second set of memory locations at the address, the memory locations in the second set being different from the memory locations in the first set of memory locations and the substitute memory locations.