← Back to Patent Explorer
US5933431A Expired / Lapsed US ⏱️ 0.0 years remaining

Frame-based modulus interleaver

Assignee: IPR 3 Pty Ltd
•
Filing: 1996-08-15
•
Granted: 1999-08-03
•
Expires: 2016-08-15
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The frame based modulus interleaver is used in a digital communications system. The interleaver uses an algorithm which insures that all of the data blocks which are present in the each input frame are output in a single output frame. This is accomplished, in accordance with the invention, by using a modulus operation to determine the location of each block which is input into the interleaver.

Inventors

  • 👤 Kenneth David Ko

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 18:13
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/27; H03M13/275

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 160 words
An improved interleaver capable of handling variable-sized frames, for use in a communications system, of the type which receives an input frame comprising a plurality of data blocks, and outputs an output frame having said data blocks interleaved therein, the interleaver comprising interleaver logic configured to ensure that each output frame has the same frame size, FS, as said input frame, wherein said logic provides that each output frame contains all of the data blocks which were contained in said input frame and wherein said logic makes use of an interleaver delay sequence of length P, wherein the increment between respective values in said delay sequence is D, and wherein said logic receives the frame size, FS, the delay sequence length, P, and the increment, D, as parameters to be used to produce the output frame having the data blocks interleaved therein, and wherein the interleaver logic is configured to ensure that the output frame has the frame size, FS.
Claim 2
Dependent Claim 160 words
An improved interleaver capable of handling variable-sized frames, for use in a communications system, of the type which receives an input frame comprising a plurality of data blocks, and outputs an output frame having said data blocks interleaved therein, the interleaver comprising interleaver logic configured to ensure that each output frame has the same frame size, FS, as said input frame, wherein said logic provides that each output frame contains all of the data blocks which were contained in said input frame and wherein said logic makes use of an interleaver delay sequence of length P, wherein the increment between respective values in said delay sequence is D, and wherein said logic receives the frame size, FS, the delay sequence length, P, and the increment, D, as parameters to be used to produce the output frame having the data blocks interleaved therein, and wherein the interleaver logic is configured to ensure that the output frame has the frame size, FS.
Claim 3
Dependent Claim 112 words
The improved interleaver of claim 1, wherein said interleaver further includes a base value, S, and an offset value, Offset, which are determined from the values of P, D and FS, such that for K equal to (FS-P*D) mod P, values of S and Offset are selected from the following table: ______________________________________ D K S Offset ______________________________________ Any P - 2 1 2 Any P - 1 0 1 Any 0 0 0 Any 1 0 D(P - 1) - 1 Any 2 P - 1 D(P - 1) - 2 1 Even (P - K/2) mod P 0 1 Odd (P - K)/2 0 none of the above not valid ______________________________________
Claim 4
Dependent Claim 64 words
The improved interleaver of claim 2, wherein said interleaver logic data blocks from a location, n, within an input frame to a location, m, in an output frame associated with said input frame, whereby all of the data blocks in said input frame are moved into said output frame, said interleaving interleaver operating in accordance with procedure set forth in the following steps: ##EQU7##
Claim 5
Dependent Claim 41 words
A de-interleaver for use with the invention defined in claim 3, said de-interleaver rearranging data blocks in a received frame of data into the sequence corresponding to the sequence which said data blocks had when they were input into said interleaver.
Claim 6
Dependent Claim 28 words
The de-interleaver of claim 4, wherein said de-interleaver logic makes use of P delay values, DelayVal( ), said delay values being determined in accordance with the following procedure:
Claim 7
Dependent Claim 52 words
The de-interleaver of claim 5, which receives a frame of data having data blocks y(n), where n ranges from 0 to FS-1, said de-interleaver logic moving a data block from position n to position m in a de-interleaver output data block, z(m), said de-interleaver logic operating in accordance with the following steps:
Claim 8
Dependent Claim 155 words
An improved de-interleaver, for use in a communications system, of the type which receives an input frame comprising a plurality of interleaved data blocks, and outputs an output frame having said interleaved data blocks de-interleaved therein, the de-interleaver logic configured to ensure that each output frame has the same frame size, FS, as said input frame and for providing that each output frame contains all of the data blocks which were contained in said input frame, wherein said de-interleaver logic makes use of a de-interleaver delay sequence of length P, wherein the increment between respective values in said delay sequence is D, and wherein said de-inteleaver logic receives the frame size, FS, the delay sequence length, P, and the increment, D, as parameters to be used to produce the output frame having the de-interleaved data blocks therein, and wherein the de-interleaver logic is configured to ensure that the output frame has the frame size, FS.
Claim 9
Dependent Claim 155 words
An improved de-interleaver, for use in a communications system, of the type which receives an input frame comprising a plurality of interleaved data blocks, and outputs an output frame having said interleaved data blocks de-interleaved therein, the de-interleaver logic configured to ensure that each output frame has the same frame size, FS, as said input frame and for providing that each output frame contains all of the data blocks which were contained in said input frame, wherein said de-interleaver logic makes use of a de-interleaver delay sequence of length P, wherein the increment between respective values in said delay sequence is D, and wherein said de-inteleaver logic receives the frame size, FS, the delay sequence length, P, and the increment, D, as parameters to be used to produce the output frame having the de-interleaved data blocks therein, and wherein the de-interleaver logic is configured to ensure that the output frame has the frame size, FS.
Claim 10
Dependent Claim 157 words
The improved de-interleaver logic of claim 7, wherein said de-interleaver further includes a base value, S, and an offset value, Offset, which are determined from the values of P, D and FS, such that for FS greater than or equal to the interleaver propagation delay of D(P-1) and for K equal to (FS-P*D) mod P, values of S and Offset are selected from the following table: ______________________________________ D K S Offset ______________________________________ Any 0 P - 1 0 Any 1 P - 1 D(P - 1) - 1 Any P - 1 D + 1 1 P - 2 2 D D(P - 1) - 2 P - 2 P - 2 0 2 1 2 P - 1 P - 2 1 P - 2 2 1 1 4n + 1 P - 2n P - (2n + 1) 1 P - (4n + 1) 2n + 1 2n none of the above not valid ______________________________________
Claim 11
Dependent Claim 61 words
The improved de-interleaver of claim 8, wherein said de-interleaver logic moves data blocks from a location, n, within an input frame to a location, m, in an output frame associated with said input frame, whereby all of the data blocks in said input frame are moved into said output frame, said de-interleaver logic operating in accordance with the following steps: ##EQU8##

References Cited (Backward Citations)

US5068752A Cited
US5367410A Cited
US5617083A Cited
US5438369A Cited
US5448555A Cited
US5563887A Cited
US5506886A Cited
US5511096A Cited
US5602685A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-08-02 2003-02-01 2003-08-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-08-02 2007-02-01 2007-08-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-08-02 2011-02-01 2011-08-03 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag