Delay circuit applied to semiconductor memory device having auto power-down function

Claim 2

A delay circuit comprising: a charge/discharge circuit for moderating a slope of change of an input signal; and a logic circuit, receiving a charge/discharge signal output from said charge/discharge circuit, for changing an output signal of said logic circuit when the charge/discharge signal exceeds a threshold value of said logic circuit, wherein: said charge/discharge circuit comprises a switch element whose one end is connected to an input of said logic circuit, and a capacitor element whose one end is connected to the other end of said switch element, wherein a switching operation of said switch element is controlled by the output signal of said logic circuit to vary a time constant of said charge/discharge circuit due to said capacitor element.

Claim 3

A delay circuit as claimed in claim 1, wherein said switch element is controlled in such a manner as to be switched OFF by the output signal of said logic circuit when the output signal of said logic circuit changes in response to said charge/discharge signal exceeding the threshold value of said logic circuit.

Claim 4

A delay circuit as claimed in claim 1, wherein there are provided a plurality of said capacitor elements whose connection to the input of said logic circuit is controlled by said switch element, and said plurality of capacitor elements are arranged in parallel with each other.

Claim 5

A delay circuit as claimed in claim 3, wherein at least one of said plurality of capacitor elements is connected at one end to the other end of said switch element and at the other end to a prescribed power supply line.

Claim 6

A delay circuit as claimed in claim 3, wherein at least one of said plurality of capacitor elements is connected at one end to the other end of said switch element and at the other end to an output of a driver circuit supplied with a prescribed control signal.

Claim 7

A delay circuit as claimed in claim 1, wherein said charge/discharge circuit is inserted in an input of said logic circuit, and further comprises a resistor element for supplying said input signal via said resistor element, and another switch element disposed in parallel with said resistor element, wherein a switching operation of said another switch element is controlled by the output signal of said logic circuit to vary the time constant of said charge/discharge circuit due to said resistor element.

Claim 8

A delay circuit as claimed in claim 6, wherein said another switch element is controlled in such a manner as to be switched ON by the output signal of said logic circuit when the output signal of said logic circuit changes in response to said charge/discharge signal exceeding the threshold value of said logic circuit.

Claim 9

A delay circuit as claimed in claim 6, wherein there are provided a plurality of said another switch elements and a plurality of said resistor elements whose short-circuiting with the input of said logic circuit is controlled by said another switch element, and said plurality of another switch elements and said plurality of resistor elements are respectively arranged in series with each other.

Claim 10

A delay circuit as claimed in claim 8, wherein said plurality of another switch elements for controlling the short-circuiting of said plurality of resistor elements are each controlled for switching, by the output signal of said logic circuit.

Claim 11

A delay circuit as claimed in claim 1, wherein said logic circuit comprises a CMOS inverter.

Claim 12

A delay circuit as claimed in claim 1, wherein said capacitor element is constituted as a MOS capacitor.

Claim 13

A semiconductor memory device having: a cell matrix having a plurality of memory cells; a data latch for latching readout data output from said cell matrix; an address transfer detection circuit for detecting an address signal change; a delay circuit, outputting a latch control signal to said data latch in accordance with an output signal of said address transfer detection circuit, for controlling said data latch to output the readout data in synchronism with the latch control signal, wherein said delay circuit comprises: a charge/discharge circuit for moderating a slope of change of an input signal; and a logic circuit, receiving a charge/discharge signal output from said charge/discharge circuit, for changing an output signal of said logic circuit when the charge/discharge signal exceeds a threshold value of said logic circuit, wherein: said charge/discharge circuit comprises a switch element whose one end is connected to an input of said logic circuit, and a capacitor element whose one end is connected to the other end of said switch element, wherein a switching operation of said switch element is controlled by the output signal of said logic circuit to vary a time constant of said charge/discharge circuit due to said capacitor element.

Claim 14

A semiconductor memory device having: a cell matrix having a plurality of memory cells; a data latch for latching readout data output from said cell matrix; an address transfer detection circuit for detecting an address signal change; a delay circuit, outputting a latch control signal to said data latch in accordance with an output signal of said address transfer detection circuit, for controlling said data latch to output the readout data in synchronism with the latch control signal, wherein said delay circuit comprises: a charge/discharge circuit for moderating a slope of change of an input signal; and a logic circuit, receiving a charge/discharge signal output from said charge/discharge circuit, for changing an output signal of said logic circuit when the charge/discharge signal exceeds a threshold value of said logic circuit, wherein: said charge/discharge circuit comprises a switch element whose one end is connected to an input of said logic circuit, and a capacitor element whose one end is connected to the other end of said switch element, wherein a switching operation of said switch element is controlled by the output signal of said logic circuit to vary a time constant of said charge/discharge circuit due to said capacitor element.

Claim 15

A semiconductor memory device as claimed in claim 12, wherein said switch element is controlled in such a manner as to be switched OFF by the output signal of said logic circuit when the output signal of said logic circuit changes in response to said charge/discharge signal exceeding the threshold value of said logic circuit.

Claim 16

A semiconductor memory device as claimed in claim 12, wherein there are provided a plurality of said capacitor elements whose connection to the input of said logic circuit is controlled by said switch element, and said plurality of capacitor elements are arranged in parallel with each other.

Claim 17

A semiconductor memory device as claimed in claim 14, wherein at least one of said plurality of capacitor elements is connected at one end to the other end of said switch element and at the other end to a prescribed power supply line.

Claim 18

A semiconductor memory device as claimed in claim 14, wherein at least one of said plurality of capacitor elements is connected at one end to the other end of said switch element and at the other end to an output of a driver circuit supplied with a prescribed control signal.

Claim 19

A semiconductor memory device as claimed in claim 12, wherein said charge/discharge circuit is inserted in an input of said logic circuit, and another comprises a resistor element for supplying said input signal via said resistor element, and a another switch element disposed in parallel with said resistor element, wherein a switching operation of said another switch element is controlled by the output signal of said logic circuit to vary the time constant of said charge/discharge circuit due to said resistor element.

Claim 20

A semiconductor memory device as claimed in claim 17, wherein said another switch element is controlled in such a manner as to be switched ON by the output signal of said logic circuit when the output signal of said logic circuit changes in response to said charge/discharge signal exceeding the threshold value of said logic circuit.

Claim 21

A semiconductor memory device as claimed in claim 17, wherein there are provided a plurality of said another switch elements and a plurality of said resistor elements whose short-circuiting with the input of said logic circuit is controlled by said another switch element, and said plurality of another switch elements and said plurality of resistor elements are respectively arranged in series with each other.

Claim 22

A semiconductor memory device as claimed in claim 19, wherein said plurality of another switch elements for controlling the short-circuiting of said plurality of resistor elements are each controlled for switching, by the output signal of said logic circuit.

Claim 23

A semiconductor memory device as claimed in claim 12, wherein said logic circuit comprises a CMOS inverter.

Claim 24

A semiconductor memory device as claimed in claim 12, wherein said capacitor element is constituted as a MOS capacitor.

Claim 25

A semiconductor memory device as claimed in claim 12, wherein said semiconductor memory device is a flash EEPROM.