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US5929628A Expired / Lapsed US ⏱️ 0.0 years remaining

Apparatus and method for performing amplitude calibration in an electronic circuit tester

Assignee: Teradyne Inc
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Filing: 1996-12-05
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Granted: 1999-07-27
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Expires: 2016-12-05
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Abstract

Abstract An electronic circuit tester, having an amplitude calibration feature, for accurately measuring signals produced by an electronic device under test, including a plurality of channels, data acquisition circuitry, an internal calibration source, and a digital filter. The internal calibration source is calibrated to a known standard. The tester then uses the internal calibration source to measure a signal amplitude error introduced by the channels and data acquisition circuitry. Next, the digital filter is automatically adjusted to correct the signal amplitude error, thereby presenting corrected data samples to a test computer for subsequent analysis.

Inventors

  • 👤 James H. Becker
  • 👤 Kenneth F. Coop

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 23:20
CPC Classifications
G; G01; G01R; G01R35/00; G01R35/005; G01R31/00; G01R31/28; G01R31/3167; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908; G01R31/3191; G01R31/3193

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 166 words
An electronic circuit tester for determining whether a device under test is functioning properly, including a plurality of channels, each channel being connected to a respective data acquisition circuit, wherein the plurality of channels and the respective data acquisition circuits contribute a signal amplitude error to at least one signal produced by the device under test, comprising: (a) means for producing a plurality of reference signals, switchably connected to each channel, the plurality of reference signals being used to determine a first amplitude response of one of the plurality of channels and the respective data acquisition circuit connected thereto; and (b) means for correcting the signal amplitude error, having a second amplitude response and being switchably connected to the respective data acquisition circuit, wherein the second amplitude response is adjustable, and wherein the one of the plurality of channels, the respective data acquisition circuit, and the means for correcting contribute no signal amplitude error to the at least one signal produced by the device under test.
Claim 2
Dependent Claim 166 words
An electronic circuit tester for determining whether a device under test is functioning properly, including a plurality of channels, each channel being connected to a respective data acquisition circuit, wherein the plurality of channels and the respective data acquisition circuits contribute a signal amplitude error to at least one signal produced by the device under test, comprising: (a) means for producing a plurality of reference signals, switchably connected to each channel, the plurality of reference signals being used to determine a first amplitude response of one of the plurality of channels and the respective data acquisition circuit connected thereto; and (b) means for correcting the signal amplitude error, having a second amplitude response and being switchably connected to the respective data acquisition circuit, wherein the second amplitude response is adjustable, and wherein the one of the plurality of channels, the respective data acquisition circuit, and the means for correcting contribute no signal amplitude error to the at least one signal produced by the device under test.
Claim 3
Dependent Claim 45 words
The electronic circuit tester as recited in claim 1, further comprising (c) means for determining an amplitude response of the channels and the respective data acquisition circuits, connected to each channel, the respective data acquisition circuits, and the means for correcting the signal amplitude error.
Claim 4
Dependent Claim 43 words
The electronic circuit tester as recited in claim 2, wherein the means for correcting the signal amplitude error comprises a digital filter, and wherein the means for determining an amplitude response comprises a test computer having at least one processor and a memory.
Claim 5
Dependent Claim 43 words
The electronic circuit tester as recited in claim 3, further comprising a first high speed data bus connected between the data acquisition circuitry and the digital filter, and a second high speed data bus connected between the digital filter and the test computer.
Claim 6
Dependent Claim 33 words
The electronic circuit tester as recited in claim 4, wherein the first high speed data bus, the digital filter, and the second high speed data bus each have the same real-time throughput rate.
Claim 7
Dependent Claim 40 words
The electronic circuit tester as recited in claim 1, wherein the plurality of reference signals have respective amplitudes and respective frequencies, and wherein each respective amplitude has a magnitude within an operating range of the channel and data acquisition circuitry.
Claim 8
Dependent Claim 29 words
The electronic circuit tester as recited in claim 6, wherein each channel samples the at least one signal produced by the device under test at a predetermined sampling frequency.
Claim 9
Dependent Claim 22 words
The electronic circuit tester as recited in claim 1, wherein the means for correcting the signal amplitude error comprises a digital filter.
Claim 10
Dependent Claim 35 words
The electronic circuit tester as recited in claim 8, wherein each channel, the data acquisition circuitry, and the digital filter in cascade is characterized by an impulse response, the impulse response being a unit sample.
Claim 11
Dependent Claim 171 words
An electronic circuit tester, including an amplitude calibration feature, for accurately measuring signals produced by a device under test, and for determining whether the device under test is functioning properly, comprising: (a) a plurality of test pins; (b) a plurality of channels switchably connected to the test pins, for driving selected test pins, and for receiving the signals appearing on other selected test pins; (c) each channel being connected to a respective data acquisition circuit, for sampling the signals to produce data samples, for converting the data samples from analog to digital form, and for storing the data samples; (d) a test computer connected to each channel and the respective data acquisition circuits, for controlling the plurality of channels and the respective data acquisition circuits, and for analyzing the data samples; and (e) an internal calibration source switchably connected to each channel, for producing a calibration signal, wherein the calibration signal is used to determine a signal amplitude error contributed by the plurality of channels and the respective data acquisition circuits.
Claim 12
Dependent Claim 171 words
An electronic circuit tester, including an amplitude calibration feature, for accurately measuring signals produced by a device under test, and for determining whether the device under test is functioning properly, comprising: (a) a plurality of test pins; (b) a plurality of channels switchably connected to the test pins, for driving selected test pins, and for receiving the signals appearing on other selected test pins; (c) each channel being connected to a respective data acquisition circuit, for sampling the signals to produce data samples, for converting the data samples from analog to digital form, and for storing the data samples; (d) a test computer connected to each channel and the respective data acquisition circuits, for controlling the plurality of channels and the respective data acquisition circuits, and for analyzing the data samples; and (e) an internal calibration source switchably connected to each channel, for producing a calibration signal, wherein the calibration signal is used to determine a signal amplitude error contributed by the plurality of channels and the respective data acquisition circuits.
Claim 13
Dependent Claim 40 words
The electronic circuit tester as recited in claim 10, further comprising a digital filter connected to the test computer and switchably connected to each respective data acquisition circuit, for presenting corrected data samples to the test computer for subsequent analysis.
Claim 14
Dependent Claim 47 words
The electronic circuit tester as recited in claim 10, further comprising a first high speed data bus switchably connected to the respective data acquisition circuitry, and connected to the digital filter, and a second high speed data bus connected between the digital filter and the test computer.
Claim 15
Dependent Claim 33 words
The electronic circuit tester as recited in claim 12, wherein the first high speed data bus, the digital filter, and the second high speed data bus each have the same real-time throughput rate.

References Cited (Backward Citations)

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EP0563676A2 Cited
EP0699914A1 Cited
EP0715177A2 Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-07-26 2003-01-25 2003-07-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-07-26 2007-01-25 2007-07-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-07-26 2011-01-25 2011-07-27 $7700.00 Window Closed / Lapsed

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