US5926430A
Expired / Lapsed
US
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Semiconductor integrated circuit device and method of activating the same
Assignee: Longitude Semiconductor SARL
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Filing: 1997-12-05
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Granted: 1999-07-20
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Expires: 2017-12-05
Abstract
Abstract A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
Inventors
- 👤 Hiromasa Noda
- 👤 Masakazu Aoki
- 👤 Youji Idei
- 👤 Kazuhiko Kajigaya
- 👤 Osamu Nagashima
- 👤 Kiyoo Itoh
- 👤 Masashi Horiguchi
- 👤 Takeshi Sakata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:16
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C5/00; G11C5/14; G11C11/4074; G11C5/147; H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016
Claims Analysis
Total Claims: 54
Claim 1
Independent Claim
117 words
A semiconductor integrated circuit comprising: a plurality of circuit blocks which perform circuit operations in response to operation control signals, respectively; a main power line; a plurality of sub-power lines provided for said plurality of circuit blocks, respectively; and a plurality of power switch circuits provided for said plurality of sub-power lines, respectively, wherein each of said plurality of power switch circuits has a plurality of switch MOSFETs provided in parallel between said main power line and a corresponding one of said plurality of sub-power lines, and wherein said plurality of power switch circuits are turned on in a stepwise manner in response to signals produced on the basis of corresponding ones of said operation control signals.
Claim 2
Dependent Claim
117 words
A semiconductor integrated circuit comprising: a plurality of circuit blocks which perform circuit operations in response to operation control signals, respectively; a main power line; a plurality of sub-power lines provided for said plurality of circuit blocks, respectively; and a plurality of power switch circuits provided for said plurality of sub-power lines, respectively, wherein each of said plurality of power switch circuits has a plurality of switch MOSFETs provided in parallel between said main power line and a corresponding one of said plurality of sub-power lines, and wherein said plurality of power switch circuits are turned on in a stepwise manner in response to signals produced on the basis of corresponding ones of said operation control signals.
Claim 3
Dependent Claim
43 words
A semiconductor integrated circuit according to claim 1, wherein said main power line is supplied with a ground level potential, and wherein said plurality of switch MOSFETs, corresponding to non-operating circuit blocks of said plurality of circuit blocks, are placed in off states.
Claim 4
Dependent Claim
19 words
A semiconductor integrated circuit according to claim 2, wherein said plurality of switch MOSFETs are N channel type MOSFETs.
Claim 5
Dependent Claim
104 words
A semiconductor integrated circuit comprising: a plurality of circuit blocks which perform circuit operations in response to operation control signals, respectively, a first voltage line, a plurality of second voltage lines provided for said plurality of circuit blocks, respectively; a plurality of switch circuits, each of which has a plurality of switch MOSFETs being provided in parallel between said first voltage line and a corresponding one of said plurality of second voltage lines; and a control circuit which controls said plurality of switch MOSFETs of said plurality of switch circuits so that said plurality of switch circuits are turned on in a stepwise manner.
Claim 6
Dependent Claim
104 words
A semiconductor integrated circuit comprising: a plurality of circuit blocks which perform circuit operations in response to operation control signals, respectively, a first voltage line, a plurality of second voltage lines provided for said plurality of circuit blocks, respectively; a plurality of switch circuits, each of which has a plurality of switch MOSFETs being provided in parallel between said first voltage line and a corresponding one of said plurality of second voltage lines; and a control circuit which controls said plurality of switch MOSFETs of said plurality of switch circuits so that said plurality of switch circuits are turned on in a stepwise manner.
Claim 7
Dependent Claim
43 words
A semiconductor integrated circuit according to claim 4, wherein said first voltage line is supplied with a ground level potential, and wherein said plurality of switch MOSFETs, corresponding to non-operating circuit blocks of said plurality of circuit blocks, are placed in off states.
Claim 8
Dependent Claim
19 words
A semiconductor integrated circuit according to claim 5, wherein said plurality of switch MOSFETs are N channel type MOSFETs.
Claim 9
Dependent Claim
89 words
A semiconductor integrated circuit comprising: a plurality of circuits; a first voltage line; a plurality of second voltage lines provided for said plurality of circuits; a plurality of switches, each of which includes a plurality of switch MOSFETs having source-drain paths provided in parallel between said first voltage line and a corresponding one of said plurality of second voltage lines; and a control circuit which controls said plurality of switch MOSFETs of said plurality of switches so that said plurality of switches are turned on in a stepwise manner.
Claim 10
Dependent Claim
89 words
A semiconductor integrated circuit comprising: a plurality of circuits; a first voltage line; a plurality of second voltage lines provided for said plurality of circuits; a plurality of switches, each of which includes a plurality of switch MOSFETs having source-drain paths provided in parallel between said first voltage line and a corresponding one of said plurality of second voltage lines; and a control circuit which controls said plurality of switch MOSFETs of said plurality of switches so that said plurality of switches are turned on in a stepwise manner.
Claim 11
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 7, wherein said plurality of switch MOSFETs, corresponding to a deactivating circuit of said plurality of circuits, are placed in off states.
Claim 12
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 8, wherein said control circuit includes a delay element provided between gates of two switch MOSFETs of said plurality of switch MOSFETs.
Claim 13
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 9, wherein said plurality of switch MOSFETs, corresponding to an activating circuit of said plurality of circuits, are placed in on states.
Claim 14
Dependent Claim
20 words
A semiconductor integrated circuit according to claim 10, wherein said first voltage line is supplied with a ground level potential.
Claim 15
Dependent Claim
103 words
A semiconductor integrated circuit comprising: a circuit block including a plurality of MOSFETs; and a circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said circuit block, wherein said circuit includes a first terminal connected to said circuit block, a second terminal supplied with a first voltage, a first switch and a second switch, wherein each of said first and second switches is provided in parallel between said first terminal and said second terminal, and wherein said first switch and said second switch are turned on in a stepwise manner in response to a control signal.
Claim 16
Dependent Claim
103 words
A semiconductor integrated circuit comprising: a circuit block including a plurality of MOSFETs; and a circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said circuit block, wherein said circuit includes a first terminal connected to said circuit block, a second terminal supplied with a first voltage, a first switch and a second switch, wherein each of said first and second switches is provided in parallel between said first terminal and said second terminal, and wherein said first switch and said second switch are turned on in a stepwise manner in response to a control signal.
Claim 17
Dependent Claim
27 words
A semiconductor integrated circuit according to claim 12, wherein said first switch is a first switch MOSFET, and wherein said second switch is a second switch MOSFET.
Claim 18
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 13, wherein said first switch MOSFET is an N channel type MOSFET, and wherein said second switch MOSFET is an N channel type MOSFET.
Claim 19
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 14, wherein said first voltage is a ground potential.
Claim 20
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 13, wherein said first switch MOSFET is a P channel type MOSFET, and wherein said second switch MOSFET is a P channel type MOSFET.
Claim 21
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 12, wherein said circuit block is a memory block.
Claim 22
Dependent Claim
18 words
A semiconductor integrated circuit according to claim 17, wherein said memory block includes a plurality of memory cells.
Claim 23
Dependent Claim
174 words
A semiconductor integrated circuit comprising: a first circuit including a plurality of MOSFETS; a first line supplied with a first voltage; a second line coupled to each of said plurality of MOSFETs; and a second circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said first circuit, wherein said second circuit includes a first switch and a second switch, wherein each of said first and second switches is provided in parallel between said first line and said second line, wherein said first and second switches are controlled to be in an OFF state when said first circuit is in a first state, and wherein said first and second switches are controlled to be in an ON state when said first circuit is in a second state, with said first and second switches being turned on in a stepwise manner so that said second switch is turned on after said first switch is turned on when said first circuit changes from said first state to said second state.
Claim 24
Dependent Claim
174 words
A semiconductor integrated circuit comprising: a first circuit including a plurality of MOSFETS; a first line supplied with a first voltage; a second line coupled to each of said plurality of MOSFETs; and a second circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said first circuit, wherein said second circuit includes a first switch and a second switch, wherein each of said first and second switches is provided in parallel between said first line and said second line, wherein said first and second switches are controlled to be in an OFF state when said first circuit is in a first state, and wherein said first and second switches are controlled to be in an ON state when said first circuit is in a second state, with said first and second switches being turned on in a stepwise manner so that said second switch is turned on after said first switch is turned on when said first circuit changes from said first state to said second state.
Claim 25
Dependent Claim
27 words
A semiconductor integrated circuit according to claim 19, wherein said first switch is a first switch MOSFET, and wherein said second switch is a second switch MOSFET.
Claim 26
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 20, wherein said first switch MOSFET in an N channel type MOSFET, and wherein said second switch MOSFET is an N channel type MOSFET.
Claim 27
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 21, further including a delay circuit coupled between the gate of said first switch MOSFET and the gate of said second switch MOSFET.
Claim 28
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 20, wherein said first switch MOSFET is a P channel type MOSFET, and wherein said second switch MOSFET is a P channel type MOSFET.
Claim 29
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 19, wherein said first circuit is a memory circuit.
Claim 30
Dependent Claim
18 words
A semiconductor integrated circuit according to claim 24, wherein said memory circuit includes a plurality of memory cells.
Claim 31
Dependent Claim
112 words
A semiconductor integrated circuit comprising: a first circuit including a plurality of MOSFETs; a first line supplied with a first voltage; a second line provided for said first circuit; and a second circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said first circuit, wherein said second circuit is coupled between said first line and said second line, and wherein, in response to a control signal, said first voltage is transmitted from said first line to said second line by said second circuit, wherein the driving ability of the second circuit in transmitting the first voltage to the second line increases in a stepwise manner.
Claim 32
Dependent Claim
112 words
A semiconductor integrated circuit comprising: a first circuit including a plurality of MOSFETs; a first line supplied with a first voltage; a second line provided for said first circuit; and a second circuit provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said first circuit, wherein said second circuit is coupled between said first line and said second line, and wherein, in response to a control signal, said first voltage is transmitted from said first line to said second line by said second circuit, wherein the driving ability of the second circuit in transmitting the first voltage to the second line increases in a stepwise manner.
Claim 33
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 26, wherein said first circuit is a memory circuit.
Claim 34
Dependent Claim
18 words
A semiconductor integrated circuit according to claim 27, wherein said memory circuit includes a plurality of memory cells.
Claim 35
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 26, wherein said second circuit includes a delay circuit.
Claim 36
Dependent Claim
150 words
A semiconductor integrated circuit comprising: a circuit block including a plurality of MOSFETS; a first line supplied with a first voltage; a second line coupled to each said plurality of MOSFETs; and a circuit including a first switch and a second switch, wherein each of said first and second switches is provided in parallel between said first line and said second line, wherein said first and second switches are controlled to be in an OFF state when said circuit block is in a first state, wherein s aid first and second switches are controlled to be in an ON state when said circuit block is in a second state, with said first and second switches being turned on in a stepwise manner so that said second switch is turned on after said first switch is turned on when said circuit block changes from said first state to said second state.
Claim 37
Dependent Claim
150 words
A semiconductor integrated circuit comprising: a circuit block including a plurality of MOSFETS; a first line supplied with a first voltage; a second line coupled to each said plurality of MOSFETs; and a circuit including a first switch and a second switch, wherein each of said first and second switches is provided in parallel between said first line and said second line, wherein said first and second switches are controlled to be in an OFF state when said circuit block is in a first state, wherein s aid first and second switches are controlled to be in an ON state when said circuit block is in a second state, with said first and second switches being turned on in a stepwise manner so that said second switch is turned on after said first switch is turned on when said circuit block changes from said first state to said second state.
Claim 38
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 30, wherein said first switch and said second switch are controlled on the basis of a control signal.
Claim 39
Dependent Claim
41 words
A semiconductor integrated circuit according to claim 30, wherein said first switch is controlled by a first control signal, and wherein said second switch is controlled by a second control signal which is a delayed signal of said first control signal.
Claim 40
Dependent Claim
33 words
A semiconductor integrated circuit according to claim 30, wherein said first state is a non-operating state of said circuit block, and wherein said second state is an operating state of said circuit block.
Claim 41
Dependent Claim
20 words
A semiconductor integrated circuit according to claim 33, wherein said non-operating state is a standby state of said circuit block.
Claim 42
Dependent Claim
33 words
A semiconductor integrated circuit according to claim 30, wherein said first state is a standby state of said circuit block, and wherein said second state is an operating state of said circuit block.
Claim 43
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 30, wherein said first switch is a first MOSFET, and wherein said second switch is a second MOSFET.
Claim 44
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 36, wherein said first MOSFET is an N channel type MOSFET, and wherein said second MOSFET is an N channel type MOSFET.
Claim 45
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 36, wherein said first MOSFET is a P channel type MOSFET, and wherein said second MOSFET is a P channel type MOSFET.
Claim 46
Dependent Claim
40 words
A semiconductor integrated circuit according to claim 36, wherein a signal of a first level is applied to a gate of said first MOSFET and a gate of said second MOSFET when said circuit block is in said first state.
Claim 47
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 39, wherein said first level is a disable level of said first and second MOSFETs.
Claim 48
Dependent Claim
39 words
A semiconductor integrated circuit according to claim 40, wherein, when said circuit block is in said second state, said gates of said first and second MOSFETs are applied with an enable level signal of said first and second MOSFETs.
Claim 49
Dependent Claim
45 words
A semiconductor integrated circuit according to claim 41, wherein said first MOSFET is an N channel type MOSFET, wherein said second MOSFET is an N channel type MOSFET, wherein said first level is a low level, and wherein said second level is a high level.
Claim 50
Dependent Claim
130 words
A semiconductor integrated circuit comprising: a first circuit including a plurality of MOSFETS; a first line supplied with a first voltage; a second line coupled to each of said plurality of MOSFETs; and a second circuit coupled between said first line and said second line, wherein said second circuit is controlled so that the current path between said first line and said second line is cut off when said first circuit is in a non-operating state, and wherein, when said first circuit changes from said non-operating state to an operating state, said first voltage is transmitted from said first line to said second line by said second circuit, wherein the driving ability of the second circuit in transmitting the first voltage to the second line increases in a stepwise manner.
Claim 51
Dependent Claim
130 words
A semiconductor integrated circuit comprising: a first circuit including a plurality of MOSFETS; a first line supplied with a first voltage; a second line coupled to each of said plurality of MOSFETs; and a second circuit coupled between said first line and said second line, wherein said second circuit is controlled so that the current path between said first line and said second line is cut off when said first circuit is in a non-operating state, and wherein, when said first circuit changes from said non-operating state to an operating state, said first voltage is transmitted from said first line to said second line by said second circuit, wherein the driving ability of the second circuit in transmitting the first voltage to the second line increases in a stepwise manner.
Claim 52
Dependent Claim
21 words
A semiconductor integrated circuit according to claim 43, wherein said second circuit is controlled on the basis of a control signal.
Claim 53
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 43, wherein the second circuit is provided in order to reduce a subthreshold leakage current of said plurality of MOSFETs of said first circuit.
Claim 54
Dependent Claim
16 words
A semiconductor integrated circuit according to claim 43, wherein said second circuit includes a delay circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-19 | 2003-01-18 | 2003-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-19 | 2007-01-18 | 2007-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-19 | 2011-01-18 | 2011-07-20 | $7700.00 | Window Closed / Lapsed |