Object oriented simulation modeling

Claim 2

A process for object oriented simulation modeling for electronic circuits comprising: executing at least one setup file for object oriented simulation of an electronic circuit wherein the execution of said setup file creates a plurality of object calls, and wherein subsequent object calls take precedence over earlier object calls using said at least one object call to create a plurality of models interconnected by a plurality of interfaces, each having a plurality of parameters within a master file in a computer directory such that a modification to a parameter of an interface carries through to each model to which it is connected within said master file, and executing a testbench simulator that uses said master file to simulate the operation of electronic circuitry.

Claim 3

A process for object oriented simulation modeling for electronic circuits as recited in claim 1 wherein the execution of said setup file creates a plurality of object calls, and wherein subsequent object calls take precedence over earlier object calls.

Claim 4

A process for object oriented simulation modeling for electronic circuits as recited in claim 1 further comprising executing at least one command for object oriented simulation of an electronic circuit after executing said setup file, said executing at least one command creating at least one object call, where subsequent object calls take precedence over earlier object calls.

Claim 5

A process for object oriented simulation modeling for electronic circuits as recited in claim 3 further comprising executing a plurality of commands for object oriented simulation of an electronic circuit after executing said setup file to create a plurality of object calls, where subsequent object calls take precedence over earlier object calls.

Claim 6

A process for object oriented simulation modeling for electronic circuits as recited in claim 1 further comprising storing said master file in a single directory of read/write memory of a computer system.

Claim 7

A computer readable media comprising computer-executable program commands for implementing the process of claim 1.

Claim 8

An object oriented simulation modeler for electronic circuits comprising: means for executing at least one setup file for object oriented simulation of an electronic circuit to create at least one object call; means for creating a master file in a directory including a plurality of models interconnected by a plurality of interfaces, each of said plurality of interfaces having at least one parameter, where said plurality of models and said plurality of interfaces were created using said at least one object call, such that a modification to a parameter of an interface carries through to each model to which it is connected; and means for executing a testbench simulator that uses said master file to simulate the operation of electronic circuitry.

Claim 9

An object oriented simulation modeler for electronic circuits comprising: means for executing at least one setup file for object oriented simulation of an electronic circuit to create at least one object call; means for creating a master file in a directory including a plurality of models interconnected by a plurality of interfaces, each of said plurality of interfaces having at least one parameter, where said plurality of models and said plurality of interfaces were created using said at least one object call, such that a modification to a parameter of an interface carries through to each model to which it is connected; and means for executing a testbench simulator that uses said master file to simulate the operation of electronic circuitry.

Claim 10

An object oriented simulation modeler for electronic circuits as in claim 7 wherein said means for executing at least one setup file creates a plurality of object calls and wherein subsequent object calls take precedence over earlier object calls.

Claim 11

An object oriented simulation modeler for electronic circuits as in claim 8 wherein said means for executing at least one setup file includes means for executing a plurality of setup files to create said plurality of object calls to create said plurality of object calls and wherein subsequent object calls take precedence over earlier object calls.

Claim 12

An object oriented simulation modeler for electronic circuits as in claim 7 further comprising means for executing at least one command for object oriented simulation of an electronic circuit after executing said setup file, said means for executing at least one command creating at least one object call, where subsequent object calls take precedence over earlier object calls.

Claim 13

A process for object oriented simulation modeling for electronic circuits as recited in claim 7 further comprising means for executing a plurality of commands for object oriented simulation of an electronic circuit after executing said setup file to create a plurality of object calls, where subsequent object calls take precedence over earlier object calls.

Claim 14

An object oriented simulation modeler for an electronic circuit comprising: a sequence of object call generators creating, as an output, a plurality of object calls, where later object calls take precedence over earlier object calls created by the object call generators; an interface generator having an output; a compiler receptive to said output of said sequence of object call generators and to said output of said interface generator, said compiler producing a master file including a plurality of models interconnected by a plurality of interfaces, each of said interfaces having at least one parameter, such that a modification to a parameter of an interface carries through to each model to which it is connected; and a testbench simulator that uses said master file to simulate the operation of electronic circuitry.

Claim 15

An object oriented simulation modeler for an electronic circuit comprising: a sequence of object call generators creating, as an output, a plurality of object calls, where later object calls take precedence over earlier object calls created by the object call generators; an interface generator having an output; a compiler receptive to said output of said sequence of object call generators and to said output of said interface generator, said compiler producing a master file including a plurality of models interconnected by a plurality of interfaces, each of said interfaces having at least one parameter, such that a modification to a parameter of an interface carries through to each model to which it is connected; and a testbench simulator that uses said master file to simulate the operation of electronic circuitry.

Claim 16

An object oriented simulation modeler for an electronic circuit as in claim 12 wherein said sequence of object call generators includes a project setup file defining a baseline project test bench and wherein said project setup file includes switches which define macros of a test bench description language for executing a series of test bench description commands.

Claim 17

An object oriented simulation modeler for an electronic circuit as in claim 12 wherein said interface generator generates a plurality of Verilog wire statements.

Claim 18

An object oriented simulation modeler for an electronic circuit as in claim 12 wherein said compiler parses a test bench description language.

Claim 19

An object oriented simulation modeler for an electronic circuit comprising: a sequence of object call generators creating, as an output, a plurality of object calls, where later object calls take precedence over earlier object calls created by the object call generators; wherein said sequence of object call generators includes: a project setup object call generator defining a baseline project test bench, said project setup object call generator further defining switches which define macros of a test bench description language for executing a series of test bench description commands; a user setup object call generator defining test bench description statements particular to a user; a local user setup object call generator defining test bench description statements particular to a directory; an embedded commands object call generator including test bench description commands embedded in a test stimulus file; and a command line object call generator allowing for test bench description language commands to be placed on a command line of said compiler; an interface generator having an output: a compiler receptive to said output of said sequence of object call generators and to said output of said interface generator, said compiler producing a master file including a plurality of models interconnected by a plurality of interfaces, each of said interfaces having at least one parameter, such that a modification to a parameter of an interface carries through to each model to which it is connected; and a testbench simulator that uses said master file to simulate the operation of electronic circuitry.

Claim 20

An object oriented simulation modeler for an electronic circuit comprising: a sequence of object call generators creating, as an output, a plurality of object calls, where later object calls take precedence over earlier object calls created by the object call generators; wherein said sequence of object call generators includes: a project setup object call generator defining a baseline project test bench, said project setup object call generator further defining switches which define macros of a test bench description language for executing a series of test bench description commands; a user setup object call generator defining test bench description statements particular to a user; a local user setup object call generator defining test bench description statements particular to a directory; an embedded commands object call generator including test bench description commands embedded in a test stimulus file; and a command line object call generator allowing for test bench description language commands to be placed on a command line of said compiler; an interface generator having an output: a compiler receptive to said output of said sequence of object call generators and to said output of said interface generator, said compiler producing a master file including a plurality of models interconnected by a plurality of interfaces, each of said interfaces having at least one parameter, such that a modification to a parameter of an interface carries through to each model to which it is connected; and a testbench simulator that uses said master file to simulate the operation of electronic circuitry.

Claim 21

A process for object oriented simulation modeling for electronic circuits comprising: compiling a test bench description language to produce simulation source files and simulation scripts to implement a test bench described in said test bench description language, said simulation source files and simulation scripts creating at least one object call; and using said at least one object call to create a plurality of models interconnected by a plurality of interfaces each having a plurality of parameters within a master file in a computer directory such that a modification to a parameter of an interface carries through to each model to which it is connected within said master file.

Claim 22

A process for object oriented simulation modeling for electronic circuits comprising: compiling a test bench description language to produce simulation source files and simulation scripts to implement a test bench described in said test bench description language, said simulation source files and simulation scripts creating at least one object call; and using said at least one object call to create a plurality of models interconnected by a plurality of interfaces each having a plurality of parameters within a master file in a computer directory such that a modification to a parameter of an interface carries through to each model to which it is connected within said master file.

Claim 23

A process for object oriented simulation modeling for electronic circuits as recited in claim 17 further comprising: executing a testbench simulator that uses said master file to simulate the operation of electronic circuitry.

Claim 24

A process for object oriented simulation modeling for electronic circuits as recited in claim 17 wherein the execution of said setup file creates a plurality of object calls, and wherein subsequent object calls take precedence over earlier object calls.

Claim 25

A process for object oriented simulation modeling for electronic circuits as recited in claim 17 further comprising executing at least one command for object oriented simulation of an electronic circuit after executing said setup file, said executing at least one command creating at least one object call, where subsequent object calls take precedence over earlier object calls.