US5922058A
Expired / Lapsed
US
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Optical transmission system for generating first-edge-based serial data bit stream by inverting control output line at mark times
Assignee: JPMorgan Chase Bank NA
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Filing: 1997-09-25
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Granted: 1999-07-13
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Expires: 2017-09-25
Abstract
Abstract Described herein is a system for transferring a binary data stream in a serial edge-based transmission format between a computer and a portable device such as the Timex® Data-Link™ watch. In the edge-based format expected by the Data-Link™ watch, individual data bits have first and second binary values which are represented by the presence or absence of signal edges at mark times which occur at a pre-selected bit rate. The system includes a computer having a digital output line which can be turned on and off by the computer at any time. The computer also has an internal timer which is programmed to generate timing signals at a frequency which is an integer multiple n of the pre-selected bit rate. An LED is operably connected to the digital output line so that the computer can switch the LED on and off at any time through the digital output line. An application program runs on the computer. The application program monitors the timing signals to transmit individual data bits of the binary data stream at corresponding n th timing signals. Specifically, the application program turns the LED on to create an optical signal edge at a particular n th timing signal if and only if the data bit corresponding to said particular n th timing signal has a `0` value. The application program then monitors the timing signals to turn the LED back off at an intermediate timing signal which occurs after said particular n th timing signal but before the next n th timing signal. The disclosed embodiment of the system includes a light wand having a distal end which is shaped to register against the face of the receiving watch. This aids the user in aligning the LED with the receiving sensor of the watch.
Inventors
- 👤 Neil S. Fishman
- 👤 Walter Helm
- 👤 Victor Shiff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:00
CPC Classifications
G; G04; G04G; G04G21/00; Y; Y10; Y10T; Y10T428/00; Y10T428/24; Y10T428/24479; Y10T428/24521; Y10T428/24529
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
205 words
A system for optically transmitting a first edge-based serial data bit stream at a predetermined bit transmission rate, wherein a first binary value is represented by the presence of an optical signal edge at a mark time and a second binary value is represented by the absence of an optical signal edge at a mark time, the system comprising: a UART having a serial output line that generates a level-based serial output signal, the UART having a control output line other than the serial output line, wherein the control output line can be inverted at any time; a first light emitting element, operably connected to the control output line of the UART, for optically transmitting the first edge-based serial data bit stream; a programmable timer that generates timing signals at a frequency which is an integer multiple of the bit transmission rate, wherein mark times occur at said bit transmission rate in coincidence with respective timing signals; programmable means responsive to said timing signals for inverting the control output line to generate optical signal edges at corresponding mark time when data bits to be transmitted at the mark times have the first binary value, the optical signal edges forming the first-edge-based serial data bit stream.
Claim 2
Independent Claim
205 words
A system for optically transmitting a first edge-based serial data bit stream at a predetermined bit transmission rate, wherein a first binary value is represented by the presence of an optical signal edge at a mark time and a second binary value is represented by the absence of an optical signal edge at a mark time, the system comprising: a UART having a serial output line that generates a level-based serial output signal, the UART having a control output line other than the serial output line, wherein the control output line can be inverted at any time; a first light emitting element, operably connected to the control output line of the UART, for optically transmitting the first edge-based serial data bit stream; a programmable timer that generates timing signals at a frequency which is an integer multiple of the bit transmission rate, wherein mark times occur at said bit transmission rate in coincidence with respective timing signals; programmable means responsive to said timing signals for inverting the control output line to generate optical signal edges at corresponding mark time when data bits to be transmitted at the mark times have the first binary value, the optical signal edges forming the first-edge-based serial data bit stream.
Claim 3
Dependent Claim
27 words
The system of claim 1, wherein the programmable means does not invert the control output line when data bits to be transmitted have a second binary value.
Claim 4
Dependent Claim
18 words
The system of claim 1, wherein the control output line of the UART is a ready-to-send control line.
Claim 5
Dependent Claim
18 words
The system of claim 1, wherein the control output line of the UART is a data-terminal-ready control line.
Claim 6
Dependent Claim
29 words
The system of claim 1, wherein the control output line remains inverted for a programmably determined time to create pulses corresponding to data bits having the first binary value.
Claim 7
Dependent Claim
152 words
The system of claim 1, wherein: the UART has a serial input line that accepts a level-based serial input signal, the UART also having a control input line other than the serial input line, wherein the control input line can be polled at any time; the system further comprises a first optical sensor, operably connected to the control input line for receiving a second serial data bit stream transmitted by a second light emitting element; and programmable means for polling said control input line at least every said mark time to detect optical signal edges in the second serial data bit stream, and wherein each data bit received in the second serial data bit stream is assigned said first binary value when an optical signal edge is detected at a particular mark time, and assigned said second binary value when an optical signal edge is not detected at the particular mark time.
Claim 8
Dependent Claim
31 words
The system of claim 6, wherein the programmable means polls the digital input line at every n and n+1 timing signals to detect the optical signal edges near said mark times.
Claim 9
Dependent Claim
28 words
The system of claim 6, wherein the programmable means polls the digital input line at every timing signal to detect the optical signal edges near said mark times.
Claim 10
Dependent Claim
23 words
The system of claim 6, wherein the first serial data bit stream is optically received by a portable device including a digital processor.
Claim 11
Dependent Claim
90 words
The system of claim 9, wherein said portable device further comprises: a second optical sensor, operably connected to a digital input line of said digital processor, for receiving said first serial data bit stream; a timer circuit for generating timing signals at a frequency of at least that of said mark time; and means for assigning, to each data bit in the received data bit stream, said first binary value when said optical signal edge is detected, and said second binary value when said optical signal edge is not detected.
Claim 12
Dependent Claim
24 words
The system of claim 10, wherein said portable device further comprises a second light emitting element for transmitting said second serial data bit stream.
Claim 13
Dependent Claim
24 words
The system of claim 1, further comprising an adapter that connects to the UART, the first light emitting element being connected to the adapter.
Claim 14
Independent Claim
205 words
A system for optically transmitting a first edge-based serial data bit stream at a predetermined bit transmission rate, wherein first binary valued in the data bit stream are represented by the presence of optical signal edges at corresponding mark times, the system comprising: a computer having a data processor, a peripheral device interface, and a programmable timer; the peripheral device interface having a serial output line that generates a level-based serial output signal, the peripheral device also having a control output line other than the serial output line, wherein the control output line can be inverted at any time; a light emitting element, operably connected to the control output line of the peripheral device interface, for optically transmitting the first edge-based serial data bit stream; the data processor being programmed to perform the following steps: setting the programmable timer to generate timing signals at a frequency which is an integer multiple of the bit transmission rate, wherein the mark time occur at said pre-selected bit transmission rate in coincidence with respective timing signals; monitoring the timing signals; inverting the control output line in response to the timing signals to generate optical signal edges at mark times when correspond data bite have the first binary value.
Claim 15
Independent Claim
205 words
A system for optically transmitting a first edge-based serial data bit stream at a predetermined bit transmission rate, wherein first binary valued in the data bit stream are represented by the presence of optical signal edges at corresponding mark times, the system comprising: a computer having a data processor, a peripheral device interface, and a programmable timer; the peripheral device interface having a serial output line that generates a level-based serial output signal, the peripheral device also having a control output line other than the serial output line, wherein the control output line can be inverted at any time; a light emitting element, operably connected to the control output line of the peripheral device interface, for optically transmitting the first edge-based serial data bit stream; the data processor being programmed to perform the following steps: setting the programmable timer to generate timing signals at a frequency which is an integer multiple of the bit transmission rate, wherein the mark time occur at said pre-selected bit transmission rate in coincidence with respective timing signals; monitoring the timing signals; inverting the control output line in response to the timing signals to generate optical signal edges at mark times when correspond data bite have the first binary value.
Claim 16
Dependent Claim
13 words
The system of claim 13, wherein the peripheral device interface is a UART.
Claim 17
Dependent Claim
55 words
A system as recited in claim 13 wherein a given mark time is followed by a subsequent mark time, the data processor being further programmed to perform a step of inverting the control output line again in response to a timing signal that occurs after the given mark time but before said subsequent mark time.
Claim 18
Dependent Claim
25 words
The system of claim 13, further comprising an adapter that connects to the peripheral device interface, the light emitting element being connected to the adapter.
Claim 19
Independent Claim
186 words
A method for optically transmitting a first edge-based serial data bit stream from a computer at a predetermined bit transmission rate, wherein first binary values in the data bit stream are represented by the presence of optical signal edges at corresponding mark times, the computer having a peripheral device interface and a programmable timer, the peripheral device interface having a serial output line that generates a level-based serial output signal, the peripheral device also having a control output line other than the serial output line, wherein the control output line can be inverted at any time, the method comprising the following steps: operably connecting a light emitting element to the control output line of the peripheral device interface; using the programmable timer of the computer to generate timing signals at a frequency which is an integer multiple of the bit transmission rate, wherein mark time occurs at said pre-selected bit transmission rate in coincidence with respective timing signals; in response to said timing signals, inverting the control output line to generate optical signal edges at mark times when corresponding data bite have the first binary value.
Claim 20
Independent Claim
186 words
A method for optically transmitting a first edge-based serial data bit stream from a computer at a predetermined bit transmission rate, wherein first binary values in the data bit stream are represented by the presence of optical signal edges at corresponding mark times, the computer having a peripheral device interface and a programmable timer, the peripheral device interface having a serial output line that generates a level-based serial output signal, the peripheral device also having a control output line other than the serial output line, wherein the control output line can be inverted at any time, the method comprising the following steps: operably connecting a light emitting element to the control output line of the peripheral device interface; using the programmable timer of the computer to generate timing signals at a frequency which is an integer multiple of the bit transmission rate, wherein mark time occurs at said pre-selected bit transmission rate in coincidence with respective timing signals; in response to said timing signals, inverting the control output line to generate optical signal edges at mark times when corresponding data bite have the first binary value.
Claim 21
Dependent Claim
28 words
The method of claim 17, further comprising a step of not inverting the control output line at mark times when corresponding data bite have a second binary value.
Claim 22
Dependent Claim
26 words
The method of claim 17, wherein the peripheral device interface is a UART, and the control output line is a ready-to-send control line of the UART.
Claim 23
Dependent Claim
26 words
The method of claim 17, wherein the peripheral device interface is a UART, and the control output line is a data-terminal-ready control line of the UART.
Claim 24
Dependent Claim
21 words
The method of claim 17, comprising a further step of leaving the control output line inverted for a programmably determined time.
Claim 25
Dependent Claim
46 words
The method of claim 17, wherein a given mark time is followed by a subsequent mark time, the method further comprising inverting the control output line again in response to a timing signal that occurs after the given mark time but before said subsequent mark time.
Claim 26
Dependent Claim
143 words
The method of claim 17, wherein the peripheral device interface has a serial input line that accepts a level-based serial input signal, the peripheral device interface also having a control input line other than the serial input line, wherein the control input line can be polled at any time, the method further comprising: operably connecting an optical sensor to the control input line of said peripheral device interface; optically receiving a second edge-based serial data bit stream at the optical sensor; and polling the control input line at least every mark time to detect optical signal edges; assigning each data bit received in the second edge-based serial data bit stream said first binary value when an optical signal edge is detected ata corresponding mark time, and said second binary value when an optical signal edge is not detected at a corresponding mark time.
Claim 27
Dependent Claim
28 words
The method of claim 23, further comprising performing the polling step at every n and n+1 said timing signals to detect optical signal edges near the mark times.
Claim 28
Dependent Claim
25 words
The method of claim 23, further comprising performing the polling step at every said timing signal to detect optical signal edges near the mark times.
Claim 29
Dependent Claim
27 words
The method of claim 23, further comprising a step of optically receiving the first edge-based serial data bit stream by a portable device including a digital processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |