Image sensor employing non-uniform A/D conversion

Claim 2

An image sensing device, comprising: an image sensor array having a plurality of imager cells arranged in at least one row and a plurality of columns, with an imager cell of any given column being coupled to a column data line of that column; and analog to digital (A/D) conversion circuitry coupled to said column data lines, and operative to convert signals on said column data lines to digitized outputs at a varying resolution, said resolution being a function of signal amplitude.

Claim 3

The image sensing device of claim 1 wherein said varying resolution is such that higher resolution is provided for signals corresponding to dark light levels than for bright light levels.

Claim 4

An image sensing device, comprising: an image sensor array having a plurality of imager cells arranged in at least one row and a plurality of columns, with an imager cell of any given column being coupled to a column data line of that column; analog to digital (A/D) conversion circuitry coupled to said column data lines, and operative to convert signals on said column data lines to digitized outputs at a varying resolution, said resolution being a function of signal amplitude; wherein said A/D conversion circuitry comprises: at least one comparator having a first input coupled to at least one of said column data lines, and a second input coupled to receive a time varying reference signal; an n-bit counter coupled to an output of said comparator; an n-bit main counter that counts in synchronism with said n-bit counter; an n-bit to m-bit converter coupled to receive an output of said n-bit main counter, where m>n, said converter nonlinearly converting n-bit codes of said main counter to m-bit codes; and an m-bit digital to analog (D/A) converter coupled to said n-bit to m-bit converter for converting said m-bit codes to said time-varying reference signal.

Claim 5

An image sensing device, comprising: an image sensor array having a plurality of imager cells arranged in at least one row and a plurality of columns, with an imager cell of any given column being coupled to a column data line of that column; analog to digital (A/D) conversion circuitry coupled to said column data lines, and operative to convert signals on said column data lines to digitized outputs at a varying resolution, said resolution being a function of signal amplitude; wherein said A/D conversion circuitry comprises: at least one comparator having a first input coupled to at least one of said column data lines, and a second input coupled to receive a time varying reference signal; an n-bit counter coupled to an output of said comparator; an n-bit main counter that counts in synchronism with said n-bit counter; an n-bit to m-bit converter coupled to receive an output of said n-bit main counter, where m>n, said converter nonlinearly converting n-bit codes of said main counter to m-bit codes; and an m-bit digital to analog (D/A) converter coupled to said n-bit to m-bit converter for converting said m-bit codes to said time-varying reference signal.

Claim 6

The image sensing device of claim 3 wherein said image sensing array has N columns, said at least one comparator comprises N comparators, with each comparator having a first input connected to a corresponding column data line and a second input coupled to receive said time varying reference signal, and said device having N of said n-bit counters, each coupled to an output of one of said comparators.

Claim 7

The image sensing device of claim 3 wherein said n-bit to m-bit converter includes a look-up table stored in memory for mapping n-bit codes to m-bit codes.

Claim 8

The image sensing device of claim 3 wherein said time varying reference signal is a voltage.

Claim 9

The image sensing device of claim 3 wherein said time varying reference signal is a current.

Claim 10

The image sensing device of claim 1, wherein said A/D conversion circuitry comprises: at least one comparator having a first input coupled to at least one of said column data lines, and a second input coupled to receive a time varying reference signal; at least one m-bit counter coupled to an output of said comparator; an m-bit main counter that counts in synchronism with said m-bit counters; an m-bit digital to analog (D/A) converter for converting an output count of said main counter to said time varying reference signal; and an m-bit to n-bit converter, where m>n, coupled to receive an output of said m-bit counter, said converter nonlinearly mapping m-bit codes to n-bit codes in a manner such that higher resolution is provided for signals on said column data lines corresponding to dark light levels than for bright light levels.

Claim 11

The image sensing device of claim 8, wherein said image sensing array has N columns, said at least one comparator comprises N comparators, each having a first input coupled to one of said column data lines and a second input coupled to receive said time varying reference signal, said at least one m-bit counter comprises N counters, each coupled to an output of one of said comparators, and further comprising a multiplexer, coupled to outputs of said M counters, for providing a time multiplexed output to said m-bit to n-bit converter.

Claim 12

The image sensing device of claim 1 wherein said device includes CMOS circuitry.

Claim 13

The image sensing device of claim 1 wherein said A/D conversion circuitry comprises a non-uniform successive approximation A/D converter.

Claim 14

The image sensing device of claim 11, wherein said non-uniform successive-approximation A/D converter comprises: a comparator for successively comparing an analog signal on one of said column data lines with a changing reference signal and providing a comparator output signal in accordance with the comparison; an n-bit successive approximation register that successively modifies an n-bit output code thereof in accordance with said comparator output signal until a least significant digit of said n-bit code is resolved; an n-bit to m-bit converter, where m>n, said n-bit to m-bit converter converting each n-bit code of said register to a corresponding m-bit code, said m-bit code being a nonlinear function of said n-bit code such that higher resolution is provided for dark light levels than for bright light levels; and an m-bit digital to analog converter for converting said m-bit code of said n-bit to m-bit converter to said changing reference signal; whereby when said least significant bit is resolved, the n-bit code of said register represents a final approximation of said analog signal.

Claim 15

The image sensing device of claim 12, further comprising an n-bit shift register for shifting out the n-bit code of said successive approximation register once the least significant digit is resolved.

Claim 16

The image sensing device of claim 12, further including a multiplexer coupled between said column data lines and said comparator for time multiplexing the signals on said column data lines.

Claim 17

An image sensing device having correlated double sampling circuitry, said image device comprising: a plurality of imager cells arranged in rows and columns, with the imager cells of any given column being coupled to a column data line of that column, and each imager cell being operable to selectively provide a first signal on an associated column data line indicative of a reset level during a first sampling interval and to provide a second signal on the associated column data line during a second sampling interval indicative of an amount of light incident upon that imager cell; an n-bit unidirectional counter operative to count in one of an up or down direction during each of said first and second sampling intervals; an n-bit to m-bit converter coupled to receive an output of said n-bit main counter, where m>n, said n-bit to m-bit converter nonlinearly mapping an n-bit count of said main counter to an m-bit count; a digital to analog converter coupled to an output of said n-bit to m-bit converter, for converting the m-bit count to a reference signal that varies nonlinearly as a function of time, said reference signal varying nonlinearly during each of said first and second sampling intervals; a plurality of comparators, each having a first input coupled to an associated one of said column data lines for receiving said first and second signals in the first and second sampling intervals, respectively, and a second input coupled to receive said time varying reference signal; and a plurality of n-bit up/down counters, each operable to count in a first direction during said first sampling interval and in an opposite direction during said second sampling interval, each of said up/down counters being responsive to an output of one of said comparators to stop counting during each of the first and second sampling intervals when the amplitude of the time varying reference signal substantially equals the amplitude of the respective first or second signal, whereby each said up/down counter provides an output representing a subtraction of one of said first or second signals from the other to complete a correlated double sampling operation.

Claim 18

An image sensing device having correlated double sampling circuitry, said image device comprising: a plurality of imager cells arranged in rows and columns, with the imager cells of any given column being coupled to a column data line of that column, and each imager cell being operable to selectively provide a first signal on an associated column data line indicative of a reset level during a first sampling interval and to provide a second signal on the associated column data line during a second sampling interval indicative of an amount of light incident upon that imager cell; an n-bit unidirectional counter operative to count in one of an up or down direction during each of said first and second sampling intervals; an n-bit to m-bit converter coupled to receive an output of said n-bit main counter, where m>n, said n-bit to m-bit converter nonlinearly mapping an n-bit count of said main counter to an m-bit count; a digital to analog converter coupled to an output of said n-bit to m-bit converter, for converting the m-bit count to a reference signal that varies nonlinearly as a function of time, said reference signal varying nonlinearly during each of said first and second sampling intervals; a plurality of comparators, each having a first input coupled to an associated one of said column data lines for receiving said first and second signals in the first and second sampling intervals, respectively, and a second input coupled to receive said time varying reference signal; and a plurality of n-bit up/down counters, each operable to count in a first direction during said first sampling interval and in an opposite direction during said second sampling interval, each of said up/down counters being responsive to an output of one of said comparators to stop counting during each of the first and second sampling intervals when the amplitude of the time varying reference signal substantially equals the amplitude of the respective first or second signal, whereby each said up/down counter provides an output representing a subtraction of one of said first or second signals from the other to complete a correlated double sampling operation.

Claim 19

The image sensor of claim 15, wherein said unidirectional counter is responsive to timing and control circuitry to count from a predetermined reference count to cause said time varying reference signal to nonlinearly ramp from a maximum level to a first lower level during the first sampling interval, said unidirectional counter being reset between the first and second sampling intervals, and counting during said second sampling interval to cause said time varying reference signal to nonlinearly ramp from said maximum level to a second level during the second sampling interval, said second level being lower than said first level.

Claim 20

The image sensor of claim 15, wherein each said comparator provides a logic level output to an associated one of said up/down counters, and each up/down counter being responsive to a predetermined state of said logic level output to stop counting.

Claim 21

A non-uniform successive-approximation analog to digital (A/D) converter, comprising: a comparator for successively comparing an analog input signal with a changing reference signal; an n-bit successive approximation register that successively modifies an n-bit output code thereof in accordance with an output signal of said comparator until a least significant digit of said n-bit code is resolved; an n-bit to m-bit converter, where m>n, said n-bit to m-bit converter converting each n-bit code of said register to a corresponding m-bit code, said m-bit code being a nonlinear function of said n-bit code; and an m-bit digital to analog converter for converting said m-bit code of said n-bit to m-bit converter to said reference signal; whereby when said least significant bit is resolved, the n-bit code of said register represents a final approximation of said analog signal.

Claim 22

A non-uniform successive-approximation analog to digital (A/D) converter, comprising: a comparator for successively comparing an analog input signal with a changing reference signal; an n-bit successive approximation register that successively modifies an n-bit output code thereof in accordance with an output signal of said comparator until a least significant digit of said n-bit code is resolved; an n-bit to m-bit converter, where m>n, said n-bit to m-bit converter converting each n-bit code of said register to a corresponding m-bit code, said m-bit code being a nonlinear function of said n-bit code; and an m-bit digital to analog converter for converting said m-bit code of said n-bit to m-bit converter to said reference signal; whereby when said least significant bit is resolved, the n-bit code of said register represents a final approximation of said analog signal.

Claim 23

The A/D converter of claim 18, further comprising an n-bit shift register for shifting out the n-bit code of said successive approximation register once the least significant digit is resolved.

Claim 24

The A/D converter of claim 18 wherein said n-bit to m-bit converter includes a look-up table stored in memory for mapping n-bit codes to m-bit codes.