US5918245A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor having a cache memory system using multi-level cache set prediction
Assignee: Oracle America Inc
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Filing: 1996-03-13
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Granted: 1999-06-29
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Expires: 2016-03-13
Abstract
Abstract A cache structure for a microprocessor which provides set-prediction information for a separate, second-level cache, and a method for improving cache accessing, are provided. In the event of a first-level cache miss, the second-level set-prediction information is used to select the set in an N-way off-chip set-associative cache. This allows a set-associative structure to be used in a second-level cache (on or off chip) without requiring a large number of traces and/or pins. Since set-prediction is used, the subsequent access time for a comparison to determine that the correct set was predicted is not in the critical timing path unless there is a mis-prediction or a miss in the second-level cache. Also, a cache memory can be partitioned into M sets, with M being chosen so that the set size is less than or equal to the page size, allowing a cache access before a TLB translation is done, further speeding the access.
Inventors
- 👤 Robert Yung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:40
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F12/0864; G06F12/0893; G06F12/0897; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054; G06F2212/00; G06F2212/60; G06F2212/608; G06F2212/6082
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
128 words
A cache memory system comprising: a plurality of entries; a plurality of tags, each tag corresponding to one of said entries; and a plurality of first set predictors each first set predictor corresponding to one of said entries each first set predictor identifying a set in a first cache memory where a predicted next entry to be accessed is predicted to be located; and a plurality of second set predictors, each second set predictor corresponding to one of said entries, each second set predictor identifying a set in a second cache memory where a predicted next entry to be accessed is predicted to be located; wherein each set in said second cache memory has a size less than or equal to the size of a page of memory.
Claim 2
Dependent Claim
128 words
A cache memory system comprising: a plurality of entries; a plurality of tags, each tag corresponding to one of said entries; and a plurality of first set predictors each first set predictor corresponding to one of said entries each first set predictor identifying a set in a first cache memory where a predicted next entry to be accessed is predicted to be located; and a plurality of second set predictors, each second set predictor corresponding to one of said entries, each second set predictor identifying a set in a second cache memory where a predicted next entry to be accessed is predicted to be located; wherein each set in said second cache memory has a size less than or equal to the size of a page of memory.
Claim 3
Dependent Claim
14 words
The memory system of claim 1 wherein a plurality of said entries are data.
Claim 4
Dependent Claim
14 words
The memory system of claim 1 wherein a plurality of said entries are instructions.
Claim 5
Dependent Claim
18 words
The memory system of claim 1 wherein a plurality of said entries include a plurality of data words.
Claim 6
Dependent Claim
17 words
The memory system of claim 1 wherein a plurality of said entries include a plurality of instructions.
Claim 7
Dependent Claim
16 words
The memory system of claim 1 wherein said second cache memory is a level two cache.
Claim 8
Dependent Claim
16 words
The memory system of claim 1 wherein said second cache memory is an Nth level cache.
Claim 9
Dependent Claim
28 words
The memory system of claim 1 wherein each logical set in said second cache memory has a size less than or equal to the size of a page.
Claim 10
Dependent Claim
25 words
The memory system of claim 1 further comprising: a cache latch for storing one of said second set predictors corresponding to a last accessed entry.
Claim 11
Dependent Claim
29 words
The memory system of claim 1 further comprising: a previous address latch for storing a last address accessed, for use in updating a set predictor for a current address.
Claim 12
Dependent Claim
43 words
The cache memory system of claim 1 wherein said tags are physical addresses, and further comprising: a translation look-aside buffer configured to translate an input virtual address in parallel with a use of said input virtual address to access said first cache memory.
Claim 13
Dependent Claim
19 words
The memory system of claim 1 wherein said first cache memory is a first level cache in a microprocessor.
Claim 14
Dependent Claim
20 words
The memory system of claim 12 wherein said second cache memory is an Nth level cache external to said microprocessor.
Claim 15
Dependent Claim
26 words
The memory system of claim 13, further comprising an Nth level cache tag memory on said microprocessor for storing tags for said external Nth level cache.
Claim 16
Dependent Claim
131 words
A computer system comprising: a system memory; a microprocessor including a level one cache memory; a level two cache memory coupled to said microprocessor; said level one cache memory including a plurality of entries, a plurality of tags, each tag corresponding to one of said entries, a plurality of first set predictors each first set predictor corresponding to one of said entries each first set predictor identifying a set in said level one cache memory where a predicted next entry to be accessed is predicted to be located; and a plurality of second set predictors, each second set predictor corresponding to one of said entries, each second set predictor identifying a set in said level two cache memory where a predicted next entry to be accessed is predicted to be located.
Claim 17
Dependent Claim
131 words
A computer system comprising: a system memory; a microprocessor including a level one cache memory; a level two cache memory coupled to said microprocessor; said level one cache memory including a plurality of entries, a plurality of tags, each tag corresponding to one of said entries, a plurality of first set predictors each first set predictor corresponding to one of said entries each first set predictor identifying a set in said level one cache memory where a predicted next entry to be accessed is predicted to be located; and a plurality of second set predictors, each second set predictor corresponding to one of said entries, each second set predictor identifying a set in said level two cache memory where a predicted next entry to be accessed is predicted to be located.
Claim 18
Independent Claim
138 words
A method for improving the accessing of a cache memory system comprising the steps of: storing a plurality of entries in a first cache memory; storing a plurality of tags, each tag corresponding to one of said entries in said first cache memory; storing a plurality of first set predictors in said first cache memory, each first set predictor corresponding to one of said entries each first set predictor identifying a set in said first cache memory where a predicted next entry to be accessed is predicted to be located; and storing a plurality of second set predictors in said first cache memory, each second set predictor corresponding to one of said entries, each second set predictor identifying a set in a second cache memory where a predicted next entry to be accessed is predicted to be located.
Claim 19
Independent Claim
138 words
A method for improving the accessing of a cache memory system comprising the steps of: storing a plurality of entries in a first cache memory; storing a plurality of tags, each tag corresponding to one of said entries in said first cache memory; storing a plurality of first set predictors in said first cache memory, each first set predictor corresponding to one of said entries each first set predictor identifying a set in said first cache memory where a predicted next entry to be accessed is predicted to be located; and storing a plurality of second set predictors in said first cache memory, each second set predictor corresponding to one of said entries, each second set predictor identifying a set in a second cache memory where a predicted next entry to be accessed is predicted to be located.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-28 | 2002-12-28 | 2003-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-28 | 2006-12-28 | 2007-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-28 | 2010-12-28 | 2011-06-29 | $7700.00 | Window Closed / Lapsed |