Universal memory element and method of programming same

Claim 3

The method of claim 1, further comprising the step of erasing data from said memory element by applying a reset energy pulse to said volume of memory material, wherein said reset energy pulse sufficient to transform said volume of memory material from said low resistance state to said high resistance state.

Claim 4

The method of claim 1, further comprising the step of: reading data from said memory element by determining whether said memory material is in said low resistance state, and if not; applying at least one additional program energy pulse to said volume of memory material sufficient to set said memory material from said high resistance state to said low resistance state; and counting said additional energy pulses.

Claim 5

The method of claim 1, wherein said energy is electrical energy.

Claim 6

The method of claim 4, wherein said electrical energy is electrical current.

Claim 7

The method of claim 4, wherein said memory element further comprises means for delivering electrical energy to said volume of memory material.

Claim 8

The method of claim 6, wherein said means for delivering is a first contact and a second contact adjoining said volume of memory material.

Claim 9

The method of programming of claim 6, wherein said means for delivering comprises at least one tapered contact, said tapered contact tapering to a peak adjoining said volume of memory material.

Claim 10

The method of programming of claim 6, wherein said means for delivering comprises at least one field emitter positioned in close proximity to said volume of memory material.

Claim 11

The method of programming of claim 6, wherein said means for delivering comprises at least one field emitter positioned within the tunneling distance of said volume of memory material.

Claim 12

The method of claim 1, wherein said energy is optical energy.

Claim 13

The method of claim 1, wherein said energy is thermal energy.

Claim 14

The method of claim 1, wherein said phase-change material includes one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof.

Claim 15

The method of claim 13, wherein said phase-change material includes at least one chalcogen element and at least one transition metal element.

Claim 16

The method of programming of claim 14, wherein said chalcogen element is selected from the group of Te, Se and mixtures or alloys thereof.

Claim 17

The method of programming of claim 15, wherein said chalcogen element is a mixture of both Te and Se.

Claim 18

The method of programming of claim 16, wherein said at least one transition metal element is selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys thereof.

Claim 21

The method of claim 18, wherein said plurality of program energy pulses is electrical energy.

Claim 22

The method of claim 19, wherein said electrical energy is electrical current.

Claim 23

The method of claim 18, wherein said energy is optical energy.

Claim 24

The method of claim 18, wherein said energy is thermal energy.

Claim 27

The method of claim 23, further including the step of reading data from said memory element, said reading step comprising the steps of: determing whether said volume of memory material is set to said low resistance state; and if not applying one or more additional program current pulses to said memory material until said memory material is set from said high resistance state to said low resistance state; and counting said additional program current pulses.

Claim 28

The method of claim 23, further including the step of erasing data from said memory element, said erasing step comprising the steps of: applying a reset current pulse to said volume of memory material, said reset current pulse sufficient to transform said memory material from said low resistance state to said high resistance state.

Claim 29

A parallel processing network comprising: (A) means for a parallel input of a plurality of data; and (B) parallel distributed processing means operative to receive and process said parallel input of said plurality of data, said processing means including: (1) a three-dimensional array of stacked planes of a plurality of unit cells; each of said unit cells is a single repetition of a repetitive, three-dimensional electrically interconnected pattern; each unit cell including: (a) data input means; (b) data output means; and (c) a multivalue-digital phase change memory element disposed so as to establish communication between said data input means and said data output means, said memory element including a chalcogenide based volume of memory material having a high resistance state and a detectably distinct low resistance state and the ability to be set from said high resistance state to said low resistance state by a set current pulse having sufficient energy, said memory material programmable to one of a plurality of detectably distinct programmed states by one or more program current pulses, each of said program current pulses insufficient to set said memory element but sufficient to modify said memory material so that accumulation with at least one additional program current pulse sets said memory element; and (2) means for establishing communication between said data input means of a first one of said unit cells in a first one of said stacked planes and said data output means of a second one of said unit cells in a second one of said stacked planes, said communication occurring through said volume of memory material of at least one of said unit cells, whereby the connection between said input means and said output means is determined by the programmed state of said memory material.

Claim 30

A parallel processing network comprising: (A) means for a parallel input of a plurality of data; and (B) parallel distributed processing means operative to receive and process said parallel input of said plurality of data, said processing means including: (1) a three-dimensional array of stacked planes of a plurality of unit cells; each of said unit cells is a single repetition of a repetitive, three-dimensional electrically interconnected pattern; each unit cell including: (a) data input means; (b) data output means; and (c) a multivalue-digital phase change memory element disposed so as to establish communication between said data input means and said data output means, said memory element including a chalcogenide based volume of memory material having a high resistance state and a detectably distinct low resistance state and the ability to be set from said high resistance state to said low resistance state by a set current pulse having sufficient energy, said memory material programmable to one of a plurality of detectably distinct programmed states by one or more program current pulses, each of said program current pulses insufficient to set said memory element but sufficient to modify said memory material so that accumulation with at least one additional program current pulse sets said memory element; and (2) means for establishing communication between said data input means of a first one of said unit cells in a first one of said stacked planes and said data output means of a second one of said unit cells in a second one of said stacked planes, said communication occurring through said volume of memory material of at least one of said unit cells, whereby the connection between said input means and said output means is determined by the programmed state of said memory material.

Claim 31

The network of claim 26, further comprising means for programming each of said plurality of unit cells to one of said programmmed states.

Claim 32

The network of claim 27, wherein said means for programming comprises means for applying an electrical signal to said volume of memory material of each of said plurality of unit cells.

Claim 33

The network of claim 28, wherein said means for applying is in electrical communication with the data input means of the corresponding unit cell.

Claim 34

The network of claim 28, wherein said means for applying is in electrical communication with the data output means of at least one other unit cell.

Claim 35

The network of claim 27, wherein said means for programming includes a field effect transistor.

Claim 36

The network of claim 31, wherein the gate of said field effect transistor is in electrical communication with the data output means of at least one other unit cell.

Claim 37

The network of claim 26, wherein each of said plurality of unit cells further includes isolation means disposed in series with said volume of memory material.

Claim 38

The network of claim 33, wherein said isolation means is a diode.

Claim 39

The network of claim 34, wherein said diode is a polycrystalline silicon diode.

Claim 40

The network of claim 34, wherein said diode is a microcrystalline diode.

Claim 41

The network of claim 26, wherein said isolation means comprises a transistor.

Claim 42

The network of claim 37, wherein said transistor is a field effect transistor.

Claim 43

The network of claim 26, wherein said means for a parallel input of a plurality of data comprises means for a parallel input of electrical data.

Claim 44

The network of claim 26, wherein said means for a parallel input of a plurality of data comprises means for a parallel input of optical data.

Claim 45

The network of claim 40, wherein the means for a parallel input of optical data further includes means for converting optical data to electrical data.

Claim 46

The network of claim 41, wherein said means for converting optical data to electrical data includes a photoresponsive body of silicon alloy material.

Claim 47

The network of claim 26, wherein said means for a parallel input of data further includes means for sensing a preselected chemical species and generating an electrical signal in response thereto.

Claim 48

The network of claim 26, wherein said chalcogenide based volume of memory material further includes one or more elements from the group consisting of carbon, silicon, germanium, tin, lead, phosphorus, arsenic, antimony, fluorine, and bismuth.

Claim 49

The network of claim 26, wherein said data input means is an excitory data input means and wherein said each unit cell further includes second data input means for the input of inhibitory data and a second chalcogenide based multivalue-digital phase change memory element, disposed so as to establish communication between said second data input means and said data output means.