US5912828A
Expired / Lapsed
US
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Equalizer filter configuration for processing real-valued and complex-valued signal samples
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-12-28
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Granted: 1999-06-15
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Expires: 2015-12-28
Abstract
Abstract An apparatus and method of implementing an equalizer filter configuration including a plurality of memory blocks and a plurality of filter blocks. The respective pluralities of memory blocks and filter blocks are coupled so that the equalizer filter configuration has the capability to process input signal samples. The input signal samples include signal samples selected from the group consisting essentially of complex-valued signal samples and real-valued signal samples.
Inventors
- 👤 Kalyan Mondal
- 👤 Kalavai Janardhan Raghunath
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:41
CPC Classifications
H; H03; H03H; H03H21/00; H03H21/0012; H03H2218/00; H03H2218/04
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
139 words
An equalizer filter configuration comprising: a plurality of filter blocks, each filter block comprising two mutually-coupled multiply-accumulate units, and each of said two mutually-coupled multiply-accumulate units comprising a multiplexer; a plurality of signal sample memory blocks, each signal sample memory block capable of supplying at least one of a complex-valued signal sample and a real-valued signal sample to the plurality of filter blocks; and a plurality of coefficient memory blocks capable of storing a plurality of coefficient signals, each coefficient signal capable of altering a response of at least one of the plurality of filter blocks; wherein the respective pluralities of signal sample memory blocks and filter blocks are coupled in said equalizer filter configuration to process input signal samples, the input signal samples comprising signal samples selected from the group comprising complex-valued signal samples and real-valued signal samples.
Claim 2
Dependent Claim
139 words
An equalizer filter configuration comprising: a plurality of filter blocks, each filter block comprising two mutually-coupled multiply-accumulate units, and each of said two mutually-coupled multiply-accumulate units comprising a multiplexer; a plurality of signal sample memory blocks, each signal sample memory block capable of supplying at least one of a complex-valued signal sample and a real-valued signal sample to the plurality of filter blocks; and a plurality of coefficient memory blocks capable of storing a plurality of coefficient signals, each coefficient signal capable of altering a response of at least one of the plurality of filter blocks; wherein the respective pluralities of signal sample memory blocks and filter blocks are coupled in said equalizer filter configuration to process input signal samples, the input signal samples comprising signal samples selected from the group comprising complex-valued signal samples and real-valued signal samples.
Claim 3
Dependent Claim
34 words
The equalizer filter configuration of claim 1, wherein said multiplexer mutually couples the multiply-accumulate units so that the multiply-accumulate units include the capability to share multiplier signals stored in the two respective multiply-accumulate units.
Claim 4
Dependent Claim
50 words
The equalizer filter configuration of claim 1, wherein said equalizer filter configuration is capable of providing equalizer filter output signals at a predetermined signal sample rate; the mutually-coupled multiply-accumulate units of said filter blocks being configured so as to operate at a clock frequency exceeding said predetermined signal sample rate.
Claim 5
Dependent Claim
21 words
The equalizer filter configuration of claim 3, wherein the clock frequency is approximately an integer multiple of the signal sample rate.
Claim 6
Dependent Claim
17 words
The equalizer filter configuration of claim 1, wherein said memory blocks comprise random access memory (RAM) units.
Claim 7
Dependent Claim
144 words
An integrated circuit comprising an equalizer filter configuration including: a plurality of filter blocks, each filter block comprising two mutually-coupled multiply-accumulate units, and each of said two mutually-coupled multiply-accumulate units comprising a multiplexer; a plurality of signal sample memory blocks, each signal sample memory block capable of supplying at least one of a complex-valued signal sample and a real-valued signal sample to the plurality of filter blocks; and a plurality of coefficient memory blocks capable of storing a plurality of coefficient signals, each coefficient signal capable of altering a response of at least one of the plurality of filter blocks; and wherein the respective pluralities of signal sample memory blocks and filter blocks are coupled in said equalizer filter configuration to process input signal samples, the input signal samples comprising signal samples selected from the group comprising complex-valued signal samples and real-valued signal samples.
Claim 8
Dependent Claim
144 words
An integrated circuit comprising an equalizer filter configuration including: a plurality of filter blocks, each filter block comprising two mutually-coupled multiply-accumulate units, and each of said two mutually-coupled multiply-accumulate units comprising a multiplexer; a plurality of signal sample memory blocks, each signal sample memory block capable of supplying at least one of a complex-valued signal sample and a real-valued signal sample to the plurality of filter blocks; and a plurality of coefficient memory blocks capable of storing a plurality of coefficient signals, each coefficient signal capable of altering a response of at least one of the plurality of filter blocks; and wherein the respective pluralities of signal sample memory blocks and filter blocks are coupled in said equalizer filter configuration to process input signal samples, the input signal samples comprising signal samples selected from the group comprising complex-valued signal samples and real-valued signal samples.
Claim 9
Dependent Claim
30 words
The integrated circuit of claim 6, wherein said multiplexer mutually couples the multiply-accumulate units so that the multiply-accumulate units selectively share multiplier signals stored in the two respective multiply-accumulate units.
Claim 10
Dependent Claim
46 words
The integrated circuit of claim 6, wherein said equalizer filter configuration is capable of providing equalizer filter output signals at a predetermined signal sample rate; the mutually-coupled multiply-accumulate units of said filter blocks substantially operate at a clock frequency exceeding said substantially predetermined signal sample rate.
Claim 11
Dependent Claim
20 words
The integrated circuit of claim 8, wherein the clock frequency is approximately an integer multiple of the signal sample rate.
Claim 12
Dependent Claim
16 words
The integrated circuit of claim 6, wherein said memory blocks comprise random access memory (RAM) units.
Claim 13
Independent Claim
201 words
A method of implementing an equalizer filter for processing complex-valued signal samples at a predetermined signal sample rate comprising the steps of: providing current and selectively delayed real-valued and imaginary-valued signal sample components to the respective multipliers of two multiply-accumulate units, wherein the current and selectively delayed real-valued and imaginary-valued signal sample components are supplied from a plurality of signal sample memory blocks, each signal sample memory block capable of supplying at least one of a complex-valued signal sample and a real-valued signal sample to a plurality of filter blocks; applying selected complex-valued coefficient signal components to said respective multipliers, wherein the selected complex-valued coefficient signal components are supplied from a plurality of coefficient memory blocks, each coefficient memory block is capable of storing a plurality of coefficient signals, and each coefficient signal is capable of altering a response of the plurality of filter blocks; and operating the two multiply-accumulate units to implement a predetermined number of taps of the equalizer filter in which a first unit of the two multiply-accumulate units produces a real-valued output signal and a second unit of the two multiply-accumulate units produces an imaginary-valued output signal, wherein each of said two multiply-accumulate units comprises a multiplexer.
Claim 14
Independent Claim
201 words
A method of implementing an equalizer filter for processing complex-valued signal samples at a predetermined signal sample rate comprising the steps of: providing current and selectively delayed real-valued and imaginary-valued signal sample components to the respective multipliers of two multiply-accumulate units, wherein the current and selectively delayed real-valued and imaginary-valued signal sample components are supplied from a plurality of signal sample memory blocks, each signal sample memory block capable of supplying at least one of a complex-valued signal sample and a real-valued signal sample to a plurality of filter blocks; applying selected complex-valued coefficient signal components to said respective multipliers, wherein the selected complex-valued coefficient signal components are supplied from a plurality of coefficient memory blocks, each coefficient memory block is capable of storing a plurality of coefficient signals, and each coefficient signal is capable of altering a response of the plurality of filter blocks; and operating the two multiply-accumulate units to implement a predetermined number of taps of the equalizer filter in which a first unit of the two multiply-accumulate units produces a real-valued output signal and a second unit of the two multiply-accumulate units produces an imaginary-valued output signal, wherein each of said two multiply-accumulate units comprises a multiplexer.
Claim 15
Dependent Claim
14 words
The method of claim 11, wherein different respective signal sample components are provided serially.
Claim 16
Dependent Claim
22 words
The method of claim 12, wherein a provided signal sample component is provided to both multiply-accumulate units substantially at the same time.
Claim 17
Dependent Claim
38 words
The method of claim 11, wherein the selected complex-valued coefficient signal components are applied to said respective multipliers via said two multiplexers, said two multiplexers being mutually-coupled to provide a signal to only one of said respective multipliers.
Claim 18
Dependent Claim
30 words
The method of claim 11, wherein the step of operating the two multiply-accumulate units comprises operating the two multiply-accumulate units at a clock frequency exceeding the predetermined signal sample rate.
Claim 19
Dependent Claim
19 words
The method of claim 15, wherein the clock frequency is an integer multiple of the predetermined signal sample rate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-06-14 | 2002-12-14 | 2003-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-14 | 2006-12-14 | 2007-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-14 | 2010-12-14 | 2011-06-15 | $7700.00 | Window Closed / Lapsed |