Trench edge rounding method and structure for trench isolation

Abstract

Abstract The present invention provides a method to achieve shallow trench isolation (STI) on the quarter-micron scale. A thin oxide layer, a thick nitride layer, a thick oxide layer and a thin nitride layer are formed sequentially on a silicon substrate. A photo-resist (PR) layer is then applied as a mask for the isolation regions. The top nitride layer, the top oxide layer and the bottom nitride layer are then etched away from the areas not covered by the PR layer. The PR layer is then removed. An isotropic oxide etch is then applied to create a recess along the bottom oxide layer. A thin oxide layer is then grown on the exposed silicon surface. A thin nitride layer is then deposited to fill the recess in the bottom oxide layer. An anisotropic nitride etch is applied to form a nitride spacer along the isolation edge. A thick oxide layer is then grown and removed. This step is repeated as necessary to obtain the desired trench slope. The silicon substrate is then etched to a predetermined depth using the oxide and nitride layers as a hard mask. The top nitride layer is also etched away. After the trench is etched, the top oxide layer is removed and thermal oxidation is applied. The trench sidewalls are then doped using implantation and/or thermal diffusion to enhance device isolation. The trench is then filled with oxide using a CVD (Chemical Vapor Deposition) process. High temperature annealing is then applied to increase the integrity of the CVD oxide film. The CVD oxide layer is then polished using CMP (Chemical Mechanical Polishing). The nitride layer is then removed. CMP or oxide etchback is then used to planarize the silicon surface.

Inventors

• 👤 Wen-Yueh Jang

Bibliographic Details