Circuit for energizing EAS marker deactivation device with DC pulses of alternating polarity

Claim 2

Apparatus for deactivating a magnetomechanical EAS marker, the apparatus comprising: a coil for generating a magnetic field to which the marker is to be exposed, said coil having a first terminal and a second terminal; a storage capacitor; a first switch connected between said storage capacitor and said first terminal of said coil; a second switch connected between said second terminal of said coil and ground; a third switch connected between said storage capacitor and said second terminal of said coil; a fourth switch connected between said first terminal of said coil and ground; and control means for controlling said first, second, third and fourth switches, said control means causing said first and second switches to be open and said third and fourth switches closed during a first sequence of time intervals, and causing said third and fourth switches to be open and said first and second switches closed during a second sequence of time intervals interleaved with said first sequence of time intervals, and causing all of said first, second, third and fourth switches to be open during a third sequence of time intervals, a respective one of said third sequence of time intervals intervening between each sequential pair of intervals of said first and second sequences.

Claim 3

Apparatus according to claim 1, the respective durations of the intervals of said first sequence are monotonically decreasing over the course of said first sequence, and the respective durations of the intervals of said second sequence are monotonically decreasing over the course of said second sequence.

Claim 4

Apparatus according to claim 2, wherein said control means includes means for generating a ramp signal, comparison means for comparing a signal level representative of a current level in said coil with said ramp signal, and means, responsive to said comparison means, for selectively terminating said intervals of said first and second sequences.

Claim 5

Apparatus according to claim 1, further comprising at least one additional coil connected in series with said coil.

Claim 6

Apparatus according to claim 1, further comprising at least one additional coil connected in parallel with said coil.

Claim 7

Apparatus according to claim 1, wherein said intervals of said third sequence are substantially longer in duration than said intervals of said first sequence, and are substantially longer in duration than said intervals of said second sequence.

Claim 8

Apparatus according to claim 1, wherein each of said first, second, third and fourth switches is constituted by a transistor switch.

Claim 9

Apparatus according to claim 7, wherein each of said first, second, third and fourth switches includes an IGBT.

Claim 12

A method according to claim 9, wherein said first pulses monotonically decrease in amplitude over a time interval and said second pulses monotonically decrease in amplitude over said time interval.

Claim 13

A method according to claim 10, wherein said time interval is substantially 150 ms in duration.

Claim 14

A method according to claim 11, where said first pulses are applied at a frequency of substantially 500 Hz, and said second pulses are applied at said frequency of substantially 500 Hz.

Claim 15

Apparatus for deactivating a magnetomechanical EAS marker, the apparatus comprising: a first coil having a first terminal and a second terminal; a second coil having a third terminal and a fourth terminal, said third terminal connected to said second terminal, said coils for generating respective magnetic fields for deactivating the marker; a storage capacitor; a first switch connected between said storage capacitor and said first terminal; a second switch connected between ground and a junction of said second and third terminals; a third switch connected between said storage capacitor and said junction of said second and third terminals; a fourth switch connected between ground and said first terminal; a fifth switch connected between said storage capacitor and said fourth terminal; a sixth switch connected between ground and said fourth terminal; and control means for controlling said first, second, third, fourth, fifth and sixth switches, said control means changing over between a first mode of operation and a second mode of operation; in said first mode of operation said control means causing said first, second, fifth and sixth switches to be open and said third and fourth switches to be closed during a first sequence of time intervals, and causing said third, fourth, fifth and sixth switches to be open and said first and second switches closed during a second sequence of time intervals interleaved with said first sequence of time intervals, and causing all of said first, second, third, fourth, fifth and sixth switches to be open during a third sequence of time intervals, a respective one of said third sequence of time intervals intervening between each sequential pair of intervals of said first and second sequences; and in said second mode of operation said control means causing said first, third, fourth and sixth switches to be open and said second and fifth switches to be closed during a fourth sequence of time intervals, and causing said first, second, fourth and fifth switches to be open and said third and sixth switches to be closed during a fifth sequence of time intervals interleaved with said fourth sequence of time intervals, and causing all of said first, second, third, fourth, fifth and sixth switches to be open during a sixth sequence of time intervals, a respective one of said sixth sequence of time intervals intervening between each sequential pair of intervals of said fourth and fifth sequences.

Claim 16

Apparatus for deactivating a magnetomechanical EAS marker, the apparatus comprising: a first coil having a first terminal and a second terminal; a second coil having a third terminal and a fourth terminal, said third terminal connected to said second terminal, said coils for generating respective magnetic fields for deactivating the marker; a storage capacitor; a first switch connected between said storage capacitor and said first terminal; a second switch connected between ground and a junction of said second and third terminals; a third switch connected between said storage capacitor and said junction of said second and third terminals; a fourth switch connected between ground and said first terminal; a fifth switch connected between said storage capacitor and said fourth terminal; a sixth switch connected between ground and said fourth terminal; and control means for controlling said first, second, third, fourth, fifth and sixth switches, said control means changing over between a first mode of operation and a second mode of operation; in said first mode of operation said control means causing said first, second, fifth and sixth switches to be open and said third and fourth switches to be closed during a first sequence of time intervals, and causing said third, fourth, fifth and sixth switches to be open and said first and second switches closed during a second sequence of time intervals interleaved with said first sequence of time intervals, and causing all of said first, second, third, fourth, fifth and sixth switches to be open during a third sequence of time intervals, a respective one of said third sequence of time intervals intervening between each sequential pair of intervals of said first and second sequences; and in said second mode of operation said control means causing said first, third, fourth and sixth switches to be open and said second and fifth switches to be closed during a fourth sequence of time intervals, and causing said first, second, fourth and fifth switches to be open and said third and sixth switches to be closed during a fifth sequence of time intervals interleaved with said fourth sequence of time intervals, and causing all of said first, second, third, fourth, fifth and sixth switches to be open during a sixth sequence of time intervals, a respective one of said sixth sequence of time intervals intervening between each sequential pair of intervals of said fourth and fifth sequences.

Claim 17

Apparatus according to claim 13, wherein each of said first, second, third, fourth, fifth and sixth switches is constituted by a transistor switch.

Claim 18

Apparatus according to claim 14, wherein each of said first, second, third, fourth, fifth and sixth switches include an IGBT.

Claim 19

A circuit for selectively energizing a coil in a device for deactivating a magnetomechanical EAS marker, the circuit comprising: a storage capacitor; a first switch for selectively connecting the storage capacitor to a first terminal of the coil; a second switch for selectively connecting the storage capacitor to a second terminal of the coil; a first current sense circuit; a third switch for selectively connecting the first terminal of the coil to the first current sense circuit; a second current sense circuit; a fourth switch for selectively connecting the second terminal of the coil to the second current sense circuit; a first comparator; means for supplying an output of said first current sense circuit to a first input of said first comparator; a second comparator; means for supplying an output of said second current sense circuit to a first input of said second comparator; means for generating a declining-ramp signal; means for supplying said declining-ramp signal in parallel to a second input of said first comparator and to a second input of said second comparator; a first D-type flip-flop; means for supplying an output of said first comparator to a clear input of said first D-type flip-flop; means for applying a first clock signal to a clock input of said first D-type flip-flop; means for supplying an output of said first D-type flip-flop in parallel as respective control signals to said second and third switches; a second D-type flip-flop; means for supplying an output of said second comparator to a clear input of said second D-type flip-flop; means for applying a second clock signal to a clock input of said second D-type flip-flop; and means for supplying an output of said second D-type flip-flop in parallel as respective control signals to said first and fourth switches.

Claim 20

A circuit for selectively energizing a coil in a device for deactivating a magnetomechanical EAS marker, the circuit comprising: a storage capacitor; a first switch for selectively connecting the storage capacitor to a first terminal of the coil; a second switch for selectively connecting the storage capacitor to a second terminal of the coil; a first current sense circuit; a third switch for selectively connecting the first terminal of the coil to the first current sense circuit; a second current sense circuit; a fourth switch for selectively connecting the second terminal of the coil to the second current sense circuit; a first comparator; means for supplying an output of said first current sense circuit to a first input of said first comparator; a second comparator; means for supplying an output of said second current sense circuit to a first input of said second comparator; means for generating a declining-ramp signal; means for supplying said declining-ramp signal in parallel to a second input of said first comparator and to a second input of said second comparator; a first D-type flip-flop; means for supplying an output of said first comparator to a clear input of said first D-type flip-flop; means for applying a first clock signal to a clock input of said first D-type flip-flop; means for supplying an output of said first D-type flip-flop in parallel as respective control signals to said second and third switches; a second D-type flip-flop; means for supplying an output of said second comparator to a clear input of said second D-type flip-flop; means for applying a second clock signal to a clock input of said second D-type flip-flop; and means for supplying an output of said second D-type flip-flop in parallel as respective control signals to said first and fourth switches.

Claim 21

A circuit according to claim 16, wherein said first and second clock signals are at substantially the same frequency and are off-set in phase from each other by substantially 180°.

Claim 22

A circuit according to claim 17, wherein said frequency of said clock signals is substantially 500 Hz.

Claim 23

A circuit according to claim 16, wherein a respective inverted output of each of said flip-flops is connected to a D-input of the respective flip-flop.

Claim 24

A circuit according to claim 16, wherein each of said switches comprises a respective insulated-gate bipolar transistor.