Operational amplification circuit capable of driving a high load

Claim 2

An operational amplification circuit comprising: a first differential amplification circuit including a first N-channel MOS transistor having a gate connected to a first input terminal, and a second N-channel MOS transistor having a gate connected to a second input terminal and generating a first signal having a voltage in accordance with a voltage difference between the first input terminal and the second input terminal; a second differential amplification circuit including a first P-channel MOS transistor having a gate connected to the first input terminal, and a second P-channel MOS transistor having a gate connected to the second input terminal and generating a second signal having a voltage in accordance with the voltage difference between the first input terminal and the second input terminal; a first level shift circuit including a third P-channel MOS transistor having a gate receiving the first signal, and a third N-channel MOS transistor, said first level shift circuit generating a third signal having a level that is shifted from the voltage of the first signal; a second level shift circuit including a fourth N-channel MOS transistor having a gate receiving the second signal, and a fourth P-channel MOS transistor, said second level shift circuit generating a fourth signal having a level that is shifted from the voltage of the second signal; a first current source circuit supplying a first predetermined current to the third N-channel MOS transistor; a second current source circuit supplying a second predetermined current to the fourth P-channel MOS transistor; and an output circuit including a fifth N-channel MOS transistor having a gate receiving the third signal and a fifth P-channel MOS transistor having a gate receiving the fourth signal, said output circuit generating an output signal in response to the third and fourth signals.

Claim 3

The operational amplification circuit according to claim 1, wherein sources of the first and second N-channel MOS transistors are connected to a third current source circuit, and wherein sources of the first and second P-channel MOS transistors are connected to a fourth current source circuit.

Claim 4

The operational amplification circuit according to claim 1, wherein said first differential amplification circuit further includes a sixth P-channel MOS transistor having a source connected to a potential source, a gate, and a drain connected to the gate, and a seventh P-channel MOS transistor having a source connected to the potential source, a gate connected to the gate of the sixth P-channel MOS transistor, and a drain.

Claim 5

The operational amplification circuit according to claim 1, wherein said second differential amplification circuit further includes a sixth N-channel MOS transistor having a source connected to a ground potential, a gate, and a drain connected to the gate, and a seventh N-channel MOS transistor having a source connected to the ground potential, a gate connected to the gate of the sixth N-channel MOS transistor, and a drain.

Claim 6

An operational amplification circuit comprising: a first differential amplification circuit including a first MOS transistor of a first conductivity type having a gate connected to a first input terminal, and a second MOS transistor of the first conductivity type having a gate connected to a second input terminal and generating a first signal having a voltage level which reflects a voltage difference between the first input terminal and the second input terminal; a second differential amplification circuit including a third MOS transistor of the first conductivity type having a gate connected to the first input terminal, and a fourth MOS transistor of the first conductivity type having a gate connected to the second input terminal and generating a second signal having a voltage level which reflects a voltage difference between the second input terminal and the first input terminal; a level shift circuit including a fifth MOS transistor of a second conductivity type having a gate receiving the first signal, and a sixth MOS transistor of the first conductivity type, said level shift circuit generating a third signal having a level that is shifted from the voltage of the first signal; a current source circuit supplying a predetermined current to the sixth MOS transistor; and an output circuit including a seventh MOS transistor of the first conductivity type having a gate receiving the third signal, and an eighth MOS transistor of the second conductivity type having a gate receiving the second signal.

Claim 7

An operational amplification circuit comprising: a first differential amplification circuit including a first MOS transistor of a first conductivity type having a gate connected to a first input terminal, and a second MOS transistor of the first conductivity type having a gate connected to a second input terminal and generating a first signal having a voltage level which reflects a voltage difference between the first input terminal and the second input terminal; a second differential amplification circuit including a third MOS transistor of the first conductivity type having a gate connected to the first input terminal, and a fourth MOS transistor of the first conductivity type having a gate connected to the second input terminal and generating a second signal having a voltage level which reflects a voltage difference between the second input terminal and the first input terminal; a level shift circuit including a fifth MOS transistor of a second conductivity type having a gate receiving the first signal, and a sixth MOS transistor of the first conductivity type, said level shift circuit generating a third signal having a level that is shifted from the voltage of the first signal; a current source circuit supplying a predetermined current to the sixth MOS transistor; and an output circuit including a seventh MOS transistor of the first conductivity type having a gate receiving the third signal, and an eighth MOS transistor of the second conductivity type having a gate receiving the second signal.

Claim 8

The operational amplification circuit according to claim 2, further comprising: a power-down circuit for controlling the seventh and eighth MOS transistors so as to be in an off-state in response to a power-down signal.

Claim 9

The operational amplification circuit according to claim 2, further comprising a phase compensation circuit connected between said first and second differential amplification circuits and said output circuit, for preventing an oscillation.

Claim 10

The operational amplification circuit according to claim 7, wherein the phase compensation circuit includes a first phase compensation circuit connected between said first differential amplification circuit and said output circuit, and a second phase compensation circuit connected between said second differential amplification circuit and said output circuit.

Claim 11

The operational amplification circuit according to claim 8, wherein the first phase compensation circuit includes a capacitor having a first terminal connected to said first differential amplifier, and a second terminal, and a ninth MOS transistor functioning as a resistor and connected between the second terminal of the capacitor and said output circuit.

Claim 12

The operational amplification circuit according to claim 8, wherein the second phase compensation circuit includes a capacitor having a first terminal connected to said second differential amplifier, and a second terminal, and a ninth MOS transistor functioning as a resistor and connected between the second terminal of the capacitor and said output circuit.

Claim 13

An operational amplification circuit comprising; a first differential amplification circuit including a first MOS transistor of a first conductivity type having a gate connected to a first input terminal, and a second MOS transistor of the first conductivity type having a gate connected to a second input terminal, the first differential amplification circuit generating a first signal having an amplified voltage in accordance with a voltage difference between the first input terminal and the second input terminal; a second differential amplification circuit including a third MOS transistor of a second conductivity type having a gate connected to the first input terminal, and a fourth MOS transistor of the second conductivity type having a gate connected to the second input terminal, the second differential amplification circuit generating a second signal having an amplified voltage in accordance with the voltage difference between the first input terminal and the second input terminal; a first level shift circuit including a fifth MOS transistor of the second conductivity type having a gate receiving the first signal, and a sixth MOS transistor of the first conductivity type, said first level shift circuit generating a third signal having a level that is shifted from the voltage of the first signal; a second level shift circuit including a seventh MOS transistor of the first conductivity type having a gate receiving the second signal, and an eighth MOS transistor of the second conductivity type, said second level shift circuit generating a fourth signal having a level that is shifted from the voltage of the second signal; a first current source circuit supplying a first predetermined current to the sixth MOS transistor; a second current source circuit supplying a second predetermined current to the eighth MOS transistor; and an output circuit including a ninth MOS transistor of the first conductivity type having a gate receiving the third signal, and a tenth MOS transistor of the second conductivity type having a gate receiving the fourth signal, said output circuit generating an output signal in response to the third and fourth signals.

Claim 14

An operational amplification circuit comprising; a first differential amplification circuit including a first MOS transistor of a first conductivity type having a gate connected to a first input terminal, and a second MOS transistor of the first conductivity type having a gate connected to a second input terminal, the first differential amplification circuit generating a first signal having an amplified voltage in accordance with a voltage difference between the first input terminal and the second input terminal; a second differential amplification circuit including a third MOS transistor of a second conductivity type having a gate connected to the first input terminal, and a fourth MOS transistor of the second conductivity type having a gate connected to the second input terminal, the second differential amplification circuit generating a second signal having an amplified voltage in accordance with the voltage difference between the first input terminal and the second input terminal; a first level shift circuit including a fifth MOS transistor of the second conductivity type having a gate receiving the first signal, and a sixth MOS transistor of the first conductivity type, said first level shift circuit generating a third signal having a level that is shifted from the voltage of the first signal; a second level shift circuit including a seventh MOS transistor of the first conductivity type having a gate receiving the second signal, and an eighth MOS transistor of the second conductivity type, said second level shift circuit generating a fourth signal having a level that is shifted from the voltage of the second signal; a first current source circuit supplying a first predetermined current to the sixth MOS transistor; a second current source circuit supplying a second predetermined current to the eighth MOS transistor; and an output circuit including a ninth MOS transistor of the first conductivity type having a gate receiving the third signal, and a tenth MOS transistor of the second conductivity type having a gate receiving the fourth signal, said output circuit generating an output signal in response to the third and fourth signals.

Claim 15

The operational amplification circuit according to claim 11, wherein sources of the first and second MOS transistors are connected to a third current source circuit, and wherein sources of the third and fourth MOS transistors are connected to a fourth current source circuit.

Claim 16

The operational amplification circuit according to claim 11, wherein said first differential amplification circuit further includes an eleventh MOS transistor of the second conductivity type having a source connected to a potential source, a gate, and a drain connected to the gate thereof and to a drain of the first MOS transistor, and a twelfth MOS transistor of the second conductivity type having a source connected to the potential source, a gate connected to the gate of the eleventh MOS transistor, and a drain connected to a drain of the second MOS transistor.

Claim 17

The operational amplification circuit according to claim 13, wherein the first signal is generated from a point at which the drains of the second and twelfth MOS transistors are connected.

Claim 18

The operational amplification circuit according to claim 11, wherein said second differential amplification circuit further includes an eleventh MOS transistor of the first conductivity type having a source connected to a ground potential, a gate, and a drain connected to the gate thereof and to a drain of the third MOS transistor, and a twelfth MOS transistor having a source connected to the ground potential, a gate connected to the gate of the eleventh MOS transistor, and a drain connected to a drain of the fourth transistor.

Claim 19

The operational amplification circuit according to claim 15, wherein the second signal is generated from a point at which the drains of the fourth and twelfth MOS transistors are connected.