US5905912A
Expired / Lapsed
US
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System for implementing peripheral device bus mastering in a computer using a list processor for asserting and receiving control signals external to the DMA controller
Assignee: Philips Semiconductors Inc
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Filing: 1996-04-08
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Granted: 1999-05-18
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Expires: 2016-04-08
Abstract
Abstract The present invention relates to a system and method for implementing peripheral device bus mastering via a general purpose list processor. The system is comprised of four main elements: a bus controller, a DMA controller, a list processor, and a device controller. The system operates under two modes of operation. The two modes arise from the two distinct modules: the DMA controller and the list processor. The first mode of operation is a single buffer transfer mode which is directly compatible with a distributed DMA model. Under this mode, distributed DMA registers within the DMA controller are programmed to transfer a single contiguous buffer of data. The second mode of operation is a multiple buffer transfer mode which uses linked lists of buffer transfer descriptors to program the distributed DMA registers within the DMA controller and initiates transfers independent of software.
Inventors
- 👤 Franklyn H. Story
- 👤 David R. Evoy
- 👤 Peter Chambers
- 👤 Lonnie Goff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:49
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
149 words
A system for implementing peripheral device bus mastering in a computer system comprising, in combination: Direct Memory Access (DMA) controller means for transferring data to and from memory of said computer system; list processor means coupled to said DMA controller means for programming said DMA controller means, generating and sending command signals, and receiving completion status after said transfer of data is complete; bus controller means coupled to said DMA controller means and said list processor means for implementing a memory data transfer request from said DMA controller means and said list processor means; and device controller means coupled to said DMA controller means and said list processor means for receiving and responding to said command signals from said list processor means, transferring said data to and from said DMA controller means, and generating and returning said completion status to said list processor means after said transfer is complete.
Claim 2
Independent Claim
149 words
A system for implementing peripheral device bus mastering in a computer system comprising, in combination: Direct Memory Access (DMA) controller means for transferring data to and from memory of said computer system; list processor means coupled to said DMA controller means for programming said DMA controller means, generating and sending command signals, and receiving completion status after said transfer of data is complete; bus controller means coupled to said DMA controller means and said list processor means for implementing a memory data transfer request from said DMA controller means and said list processor means; and device controller means coupled to said DMA controller means and said list processor means for receiving and responding to said command signals from said list processor means, transferring said data to and from said DMA controller means, and generating and returning said completion status to said list processor means after said transfer is complete.
Claim 3
Dependent Claim
26 words
A system for implementing peripheral device bus mastering in accordance with claim 1 wherein said DMA controller means is implemented as a distributed DMA target slice.
Claim 4
Dependent Claim
26 words
A system for implementing peripheral device bus mastering in accordance with claim 1 wherein said list processor means is an embedded microcontroller in said computer system.
Claim 5
Dependent Claim
26 words
A system for implementing peripheral device bus mastering in accordance with claim 1 wherein said list processor means is a host CPU of said computer system.
Claim 6
Dependent Claim
41 words
A system for implementing peripheral device bus mastering in accordance with claim 1 further comprising data buffer descriptor means created in said memory of said computer system for describing a data transfer that said list processor means initiates, controls, and completes.
Claim 7
Dependent Claim
25 words
A system for implementing peripheral device bus mastering in accordance with claim 1 wherein said device controller means is a Universal Serial Bus (USB) controller.
Claim 8
Dependent Claim
25 words
A system for implementing peripheral device bus mastering in accordance with claim 1 wherein said device controller means is an Infrared Data Association (IrDA) controller.
Claim 9
Dependent Claim
27 words
A system for implementing peripheral device bus mastering in accordance with claim 1 wherein said device controller means is an Integrated Drive Electronics (IDE) hard disk controller.
Claim 10
Dependent Claim
27 words
A system for implementing peripheral device bus mastering in accordance with claim 1 wherein said device controller means is an Extended Capabilities Port (ECP) parallel port controller.
Claim 11
Independent Claim
200 words
A method for implementing peripheral device bus mastering comprising the steps of: providing a system for implementing peripheral device bus mastering wherein said step of providing a system for implementing peripheral device bus mastering further comprises the steps of: providing Direct Memory Access (DMA) controller means for transferring data to and from memory; providing list processor means coupled to said DMA controller means for programming said DMA controller means, generating and sending command signals, and receiving completion status after said transfer of data is complete; providing bus controller means coupled to said DMA controller means and said list processor means for implementing a memory data transfer request from said DMA controller means and said list processor means; and providing device controller means coupled to said DMA controller means and said list processor means for receiving and responding to said command signals from said list processor means, transferring said data to and from said DMA controller means, and generating and returning said completion status to said list processor means after said transfer is complete; transferring data under a first mode of operation; and transferring said data under a second mode of operation if said first mode of operation is not used.
Claim 12
Independent Claim
200 words
A method for implementing peripheral device bus mastering comprising the steps of: providing a system for implementing peripheral device bus mastering wherein said step of providing a system for implementing peripheral device bus mastering further comprises the steps of: providing Direct Memory Access (DMA) controller means for transferring data to and from memory; providing list processor means coupled to said DMA controller means for programming said DMA controller means, generating and sending command signals, and receiving completion status after said transfer of data is complete; providing bus controller means coupled to said DMA controller means and said list processor means for implementing a memory data transfer request from said DMA controller means and said list processor means; and providing device controller means coupled to said DMA controller means and said list processor means for receiving and responding to said command signals from said list processor means, transferring said data to and from said DMA controller means, and generating and returning said completion status to said list processor means after said transfer is complete; transferring data under a first mode of operation; and transferring said data under a second mode of operation if said first mode of operation is not used.
Claim 13
Dependent Claim
95 words
The method of claim 10 wherein said step of transferring data under a first mode of operation further comprises the steps of: providing DMA registers within said DMA controller means; providing a start address to locate data to be transferred; providing a transfer count to define a size of a single contiguous buffer of data; transferring said single contiguous buffer of data as defined by said DMA registers to said device controller; sending a signal to indicate when transfer of said data is complete; and programming said DMA registers for a next transfer of data.
Claim 14
Dependent Claim
87 words
The method of claim 10 wherein said step of transferring data under a second mode of operation further comprises the steps of: providing a plurality of data buffer descriptor means coupled to said list processor means for programming DMA registers; reading a data buffer descriptor means pointed to by a descriptor address register; programming said DMA registers for transferring data; transferring said data as defined by said DMA registers to said device controller means; and sending a signal to indicate when transfer of said data is complete.
Claim 15
Dependent Claim
16 words
The method of claim 12 wherein said plurality of data buffer descriptor means are periodic descriptors.
Claim 16
Dependent Claim
16 words
The method of claim 12 wherein said plurality of data buffer descriptor means are aperiodic descriptors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-17 | 2002-11-16 | 2003-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-17 | 2006-11-16 | 2007-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-17 | 2010-11-16 | 2011-05-18 | $7700.00 | Window Closed / Lapsed |