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US5902132A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device including a process of forming a contact hole

Assignee: Oki Electric Industry Co Ltd
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Filing: 1997-04-29
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Granted: 1999-05-11
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Expires: 2017-04-29
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Abstract

Abstract A relatively easy manufacturing method of a semiconductor device enabling a contact hole 25 to be formed reliably by self alignment without exposing a gate 11, wherein a plug 20 is adopted to protect an etching stopper film 16 from an etching gas when a preliminary opening 24 is formed by etching an insulating film 22 having an electrical insulating etching stopper film 16 embedded therein.

Inventors

  • 👤 Toshiro Mitsuhashi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 17:46
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; Y; Y10; Y10S; Y10S148/00; Y10S148/02

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 242 words
A method of manufacturing a semiconductor device, including a process of forming a contact hole, opened above a semiconductor substrate between a pair of gates, in an insulating film having embedded therein said pair of gates formed spaced apart from each other on said semiconductor substrate, comprising the steps of: forming an etching stopper film having electrical insulating properties to cover said gates formed on said semiconductor substrate and exposed surfaces of said semiconductor device; filling with a plug a recess covered with said etching stopper film and defined between said gates by said gates; forming said insulating film to have said etching stopper film and said plug formed partially on said etching stopper film embedded therein; forming in said insulating film a preliminary opening having said plug exposed thereto by etching said insulating film with a first etching gas having an insulating film/plug selectivity ratio and with a mask; removing said plug exposed to said preliminary opening with a second etching gas having a selectivity ratio of said plug to said insulating film and said etching stopper film, higher than said selectivity ratio of said first etching gas; and removing that portion of said stopper film which has been exposed by said plug etching step and which is located on said semiconductor substrate, with a third etching gas having a selectivity ratio of said etching stopper film to said semiconductor substrate, thereby forming said contact hole open above said semiconductor substrate.
Claim 2
Independent Claim 242 words
A method of manufacturing a semiconductor device, including a process of forming a contact hole, opened above a semiconductor substrate between a pair of gates, in an insulating film having embedded therein said pair of gates formed spaced apart from each other on said semiconductor substrate, comprising the steps of: forming an etching stopper film having electrical insulating properties to cover said gates formed on said semiconductor substrate and exposed surfaces of said semiconductor device; filling with a plug a recess covered with said etching stopper film and defined between said gates by said gates; forming said insulating film to have said etching stopper film and said plug formed partially on said etching stopper film embedded therein; forming in said insulating film a preliminary opening having said plug exposed thereto by etching said insulating film with a first etching gas having an insulating film/plug selectivity ratio and with a mask; removing said plug exposed to said preliminary opening with a second etching gas having a selectivity ratio of said plug to said insulating film and said etching stopper film, higher than said selectivity ratio of said first etching gas; and removing that portion of said stopper film which has been exposed by said plug etching step and which is located on said semiconductor substrate, with a third etching gas having a selectivity ratio of said etching stopper film to said semiconductor substrate, thereby forming said contact hole open above said semiconductor substrate.
Claim 3
Dependent Claim 24 words
A method of manufacturing a semiconductor device according to claim 1, wherein said plug has a shoulder portion extending above said pair of gates.
Claim 4
Dependent Claim 96 words
A method of manufacturing a semiconductor device according to claim 2, wherein a protective film is formed on the top portion of each gate, wherein said etching stopper film formed to cover said gates and said exposed surfaces of said semiconductor substrate also covers said protective film on the top portion of each gate, wherein said shoulder portion of said plug is removed before said plug is embedded in said insulating film, and said plug now shaped such that its height is almost the same as the pair of gates is embedded in the insulating film.
Claim 5
Dependent Claim 35 words
A method of manufacturing a semiconductor device according to claim 3, wherein said semiconductor substrate is a silicon crystal substrate, said plug is made of polysilicon, and said insulating film is made of silicon oxide.
Claim 6
Dependent Claim 30 words
A method of manufacturing a semiconductor device according to claim 4, wherein said protective film is a silicon oxide film, and said etching stopper film is a silicon nitride film.
Claim 7
Dependent Claim 30 words
A method of manufacturing a semiconductor device according to claim 4, wherein said protective film is a silicon nitride film, and said etching stopper film is a silicon oxide film.
Claim 8
Dependent Claim 48 words
A method of manufacturing a semiconductor device according to claim 5, wherein said first etching gas is a plasma gas, including CF4, CHF3 and Ar, said second etching gas is a plasma gas, including SF6, and said third etching gas is a plasma gas, including CF4 and O2.
Claim 9
Dependent Claim 49 words
A method of manufacturing a semiconductor device according to claim 6, wherein said first etching gas is a plasma gas, including CF4, CHF3 and Ar, said second etching gas is a plasma gas, including SF6, and said third etching gas is a plasma gas, including CF4, CHF3 and Ar.

References Cited (Backward Citations)

US4997790A Cited
US5705427A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-05-10 2002-11-09 2003-05-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-05-10 2006-11-09 2007-05-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-05-10 2010-11-09 2011-05-11 $7700.00 Window Closed / Lapsed

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