Method of manufacturing a semiconductor device having various types of MOSFETS

Claim 1

A method of manufacturing a semiconductor device including on a single chip a non-volatile memory element, an input protecting element and a logic circuit element, comprising the steps of: (a) forming a first gate of a first MOS transistor for said non-volatile memory element, a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type; (b) simultaneously injecting a first impurity of a second conductivity type in said substrate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element, said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element; (d) after said step (c), injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure; (e) removing said first mask, and forming first side wall insulating films on sidewalls of said third gate of said third MOS transistor for said logic circuit element; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure.

Claim 2

A method of manufacturing a semiconductor device including on a single chip a non-volatile memory element, an input protecting element and a logic circuit element, comprising the steps of: (a) forming a first gate of a first MOS transistor for said non-volatile memory element, a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type; (b) simultaneously injecting a first impurity of a second conductivity type in said substrate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element, said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element; (d) after said step (c), injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure; (e) removing said first mask, and forming first side wall insulating films on sidewalls of said third gate of said third MOS transistor for said logic circuit element; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure.