US5897653A
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Data tracing apparatus
Assignee: Renesas Design Corp
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Filing: 1996-12-17
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Granted: 1999-04-27
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Expires: 2016-12-17
Abstract
Abstract A data tracing apparatus includes a data storing unit having a first area and a second area, for storing data corresponding to a predetermined number of bus cycles, a data writing/reading controlling unit for writing data alternatively to the first area and the second area for each of the predetermined number of bus cycles and for reading data stored in an area which is not subject to writing and within first area and the second area, reading being faster than writing, a dynamic memory for successively storing data read from the data storing unit by the data writing/reading controlling unit, and a refreshing unit for refreshing the dynamic memory after reading by the data writing/reading controlling unit.
Inventors
- 👤 Naohisa Tashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 00:50
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/22; G06F11/26; G06F11/261; G06F11/30; G06F11/34; G06F11/3466; G06F11/3476; G06F11/348; G06F11/349
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
184 words
A data tracing apparatus for successively storing trace data concerning execution of a program by a target microcomputer for each bus cycle, the apparatus comprising: data storing means having a first memory area and a second memory area for storing trace data concerning operations of a target microcomputer in executing a program to be debugged, each of the first and second memory areas storing trace data corresponding to n bus cycles, n being a natural number; data writing/reading controlling means for, during a first time period, writing trace data to the first memory area and reading trace data from the second memory area for n bus cycles and for, during a second time period, after the first time period, reading trace data stored in the first memory area and writing trace data to the second memory area for n bus cycles, the reading being faster than the writing; a dynamic memory for successively storing trace data read from the data storing means by the data writing/reading controlling means; and refreshing means for refreshing the dynamic memory after reading by the data writing/reading controlling means.
Claim 2
Dependent Claim
184 words
A data tracing apparatus for successively storing trace data concerning execution of a program by a target microcomputer for each bus cycle, the apparatus comprising: data storing means having a first memory area and a second memory area for storing trace data concerning operations of a target microcomputer in executing a program to be debugged, each of the first and second memory areas storing trace data corresponding to n bus cycles, n being a natural number; data writing/reading controlling means for, during a first time period, writing trace data to the first memory area and reading trace data from the second memory area for n bus cycles and for, during a second time period, after the first time period, reading trace data stored in the first memory area and writing trace data to the second memory area for n bus cycles, the reading being faster than the writing; a dynamic memory for successively storing trace data read from the data storing means by the data writing/reading controlling means; and refreshing means for refreshing the dynamic memory after reading by the data writing/reading controlling means.
Claim 3
Dependent Claim
85 words
The data tracing apparatus according to claim 1, wherein the data storing means includes a first memory corresponding to the first memory area and a second memory corresponding to the second memory area, and wherein the data writing/reading controlling means has a selector, receiving an output signal from the first memory and an output signal from the second memory, for selecting the output signal from the first memory and the second memory subject to reading and for outputting the selected signal to the dynamic memory.
Claim 4
Dependent Claim
21 words
The data tracing apparatus according to claim 2, wherein the first memory and the second memory each comprise a static memory.
Claim 5
Dependent Claim
118 words
A data tracing apparatus comprising: a target microcomputer for executing a program to be debugged and for outputting trace data concerning operations of the target microcomputer in executing the program; a first-in first-out memory coupled to the target microcomputer for storing trace data; data writing/reading controlling means for writing trace data to the first-in first-out memory and for reading trace data from the first-in first-out memory for n bus cycles, n being a natural number, the reading being faster than the writing; a dynamic memory for successively storing trace data read from the first-in first-out memory by the data writing/reading controlling means; and refreshing means for refreshing the dynamic memory after reading by the data writing/reading controlling means.
Claim 6
Dependent Claim
118 words
A data tracing apparatus comprising: a target microcomputer for executing a program to be debugged and for outputting trace data concerning operations of the target microcomputer in executing the program; a first-in first-out memory coupled to the target microcomputer for storing trace data; data writing/reading controlling means for writing trace data to the first-in first-out memory and for reading trace data from the first-in first-out memory for n bus cycles, n being a natural number, the reading being faster than the writing; a dynamic memory for successively storing trace data read from the first-in first-out memory by the data writing/reading controlling means; and refreshing means for refreshing the dynamic memory after reading by the data writing/reading controlling means.
Claim 7
Dependent Claim
41 words
The data tracing apparatus according to claim 1 comprising a target microcomputer coupled to the data storing means for executing the program to be debugged and for outputting trace data concerning the operations of the target microcomputer in executing the program.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-26 | 2002-10-26 | 2003-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-26 | 2006-10-26 | 2007-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-26 | 2010-10-26 | 2011-04-27 | $7700.00 | Window Closed / Lapsed |