US5896552A
Expired / Lapsed
US
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Bus analyzer for capturing bus signals at a predetermined rate and upon assertion of a data valid signal
Assignee: National Instruments Corp
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Filing: 1997-08-22
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Granted: 1999-04-20
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Expires: 2017-08-22
Abstract
Abstract A GPIB system for capturing GPIB signals at a predetermined rate and upon valid transitions of the data valid signal. A first sampling circuit samples the GPIB at the predetermined rate and a second sampling circuit samples the GPIB with transitions of the data valid signal. Capture logic preferably includes data valid logic for monitoring the data valid signal to assure valid transitions. The capture logic also preferably includes select logic for selecting between the GPIB signals sampled at the predetermined rate and upon assertion of the data valid signal, where data valid signal transitions preferably have higher priority. The capture logic monitors the sampled GPIB signals and the data valid logic to enable a first-in, first-out buffer to capture sampled data upon predetermined capture conditions and upon transitions of the data valid signal. In this manner, data signal transitions which might otherwise be missed by the predetermined sampling rate are sampled and captured. Furthermore, a counter circuit is implemented to provide a time-stamp value into the buffer after each captured data value. The capture logic asserts a time-stamp signal to select the time-stamp value and also enables the buffer to capture time-stamp value into the buffer.
Inventors
- 👤 Robert C. Kowert
- 👤 Andrew Thomson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 13:41
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3177
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
147 words
A device for capturing signals on a bus into a buffer, wherein the bus includes a data valid signal for indicating when data is valid on the bus, the device comprising: a first sampling circuit coupled to the bus, wherein said first sampling circuit samples the bus synchronously to a clock source and provides first samples of the bus; a second sampling circuit coupled to the bus, wherein said second sampling circuit samples the bus asynchronously to the clock source upon assertion of the data valid signal and provides second samples of the bus; and capture logic receiving said first samples and said second samples, wherein said capture logic selects between providing said first samples and said second samples to the buffer, wherein said second samples are selected to be provided to the buffer to capture signal transitions that may not be captured by said first samples.
Claim 2
Independent Claim
147 words
A device for capturing signals on a bus into a buffer, wherein the bus includes a data valid signal for indicating when data is valid on the bus, the device comprising: a first sampling circuit coupled to the bus, wherein said first sampling circuit samples the bus synchronously to a clock source and provides first samples of the bus; a second sampling circuit coupled to the bus, wherein said second sampling circuit samples the bus asynchronously to the clock source upon assertion of the data valid signal and provides second samples of the bus; and capture logic receiving said first samples and said second samples, wherein said capture logic selects between providing said first samples and said second samples to the buffer, wherein said second samples are selected to be provided to the buffer to capture signal transitions that may not be captured by said first samples.
Claim 3
Dependent Claim
24 words
The device as recited in claim 1, wherein said first and second sampling circuits each include a set of flip-flops for sampling bus signals.
Claim 4
Dependent Claim
15 words
The device as recited in claim 1, wherein the buffer comprises a first-in, first-out buffer.
Claim 5
Dependent Claim
17 words
The device as recited in claim 1, wherein the bus comprises a General Purpose Interface Bus (GPIB).
Claim 6
Dependent Claim
41 words
The device as recited in claim 1, wherein said capture logic further comprises select logic for determining capture conditions for which said second samples should be selected to be provided to the buffer to ensure valid signal transitions are not missed.
Claim 7
Dependent Claim
29 words
The device as recited in claim 5, wherein said capture conditions for which said second samples should be selected, result when changes in the bus signals match predetermined conditions.
Claim 8
Dependent Claim
58 words
The device as recited in claim 1, further comprising: a counter circuit for providing a time-stamp value; wherein said capture logic further receives said time-stamp value; and wherein said capture logic further comprises control logic for controlling when said first and second samples are provided to said buffer and when said time-stamp value is provided to said buffer.
Claim 9
Dependent Claim
32 words
The device as recited in claim 7, wherein said control logic operates to provide said time-stamp value to said buffer after each said first or second sample is provided to said buffer.
Claim 10
Dependent Claim
23 words
The device as recited in claim 8, wherein said counter circuit is reset after each said time-stamp value is provided to said buffer.
Claim 11
Dependent Claim
17 words
The device as recited in claim 7, wherein the bus comprises a General Purpose Interface Bus (GPIB).
Claim 12
Dependent Claim
177 words
A GPIB system, comprising: a GPIB having signals including a data valid signal; a GPIB controller coupled to said GPIB, wherein said GPIB controller performs controller functions as defined in the GPIB (IEEE 488) standard; at least one GPIB device coupled to said GPIB for communicating on said GPIB; a GPIB analyzer coupled to said GPIB, said analyzer comprising: a first sampling circuit coupled to said GPIB, wherein said first sampling circuit samples the bus synchronously to a clock source and provides first samples of said GPIB; a second sampling circuit coupled to said GPIB, wherein said second sampling circuit samples said GPIB asynchronously to the clock source upon assertion of said data valid signal and provides second samples of said GPIB; a buffer; and capture logic receiving said first samples and said second samples, wherein said capture logic selects between providing said first samples and said second samples to said buffer, wherein said second samples are selected to be provided to said buffer to capture signal transitions that may not be captured by said first samples.
Claim 13
Dependent Claim
177 words
A GPIB system, comprising: a GPIB having signals including a data valid signal; a GPIB controller coupled to said GPIB, wherein said GPIB controller performs controller functions as defined in the GPIB (IEEE 488) standard; at least one GPIB device coupled to said GPIB for communicating on said GPIB; a GPIB analyzer coupled to said GPIB, said analyzer comprising: a first sampling circuit coupled to said GPIB, wherein said first sampling circuit samples the bus synchronously to a clock source and provides first samples of said GPIB; a second sampling circuit coupled to said GPIB, wherein said second sampling circuit samples said GPIB asynchronously to the clock source upon assertion of said data valid signal and provides second samples of said GPIB; a buffer; and capture logic receiving said first samples and said second samples, wherein said capture logic selects between providing said first samples and said second samples to said buffer, wherein said second samples are selected to be provided to said buffer to capture signal transitions that may not be captured by said first samples.
Claim 14
Dependent Claim
25 words
The GPIB system as recited in claim 11, wherein said first and second sampling circuits each include a set of flip-flops for sampling bus signals.
Claim 15
Dependent Claim
16 words
The GPIB system as recited in claim 11, wherein said buffer comprises a first-in, first-out buffer.
Claim 16
Dependent Claim
42 words
The GPIB system as recited in claim 11, wherein said capture logic further comprises select logic for determining capture conditions for which said second samples should be selected to be provided to the buffer to ensure valid signal transitions are not missed.
Claim 17
Dependent Claim
30 words
The GPIB system as recited in claim 14, wherein said capture conditions for which said second samples should be selected, result when changes in the GPIB signals match predetermined conditions.
Claim 18
Dependent Claim
63 words
The GPIB system as recited in claim 11, wherein said GPIB analyzer further comprises: a counter circuit for providing a time-stamp value; wherein said capture logic further receives said time-stamp value; and wherein said capture logic further comprises control logic for controlling when said first and second samples are provided to said buffer and when said time-stamp value is provided to said buffer.
Claim 19
Dependent Claim
33 words
The GPIB system as recited in claim 16, wherein said control logic operates to provide said time-stamp value to said buffer after each said first or second sample is provided to said buffer.
Claim 20
Dependent Claim
24 words
The GPIB system as recited in claim 17, wherein said counter circuit is reset after each said time-stamp value is provided to said buffer.
Claim 21
Independent Claim
104 words
A method of capturing bus signals, wherein the bus signals include a data valid signal, the method comprising; sampling the bus signals at a predetermined rate to provide first samples; sampling the bus signals upon assertions of said data valid signal substantially concurrently with said sampling the bus signals at a predetermined rate, to provide second samples; choosing between said first samples and said second samples to capture into a buffer, wherein said second samples are chosen when conditions indicate said first samples may have missed a valid bus signal transition; and capturing said samples from said choosing into a buffer upon predetermined conditions.
Claim 22
Independent Claim
104 words
A method of capturing bus signals, wherein the bus signals include a data valid signal, the method comprising; sampling the bus signals at a predetermined rate to provide first samples; sampling the bus signals upon assertions of said data valid signal substantially concurrently with said sampling the bus signals at a predetermined rate, to provide second samples; choosing between said first samples and said second samples to capture into a buffer, wherein said second samples are chosen when conditions indicate said first samples may have missed a valid bus signal transition; and capturing said samples from said choosing into a buffer upon predetermined conditions.
Claim 23
Dependent Claim
44 words
The method as recited in claim 19, further comprising: measuring elapsed time after each sample from said choosing is captured into said buffer, to provide an elapsed time value; and inserting said elapsed time value into said buffer after each sample from said choosing.
Claim 24
Dependent Claim
19 words
The method as recited in claim 20, wherein said bus signals are defined according to the IEEE 488 specification.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-19 | 2002-10-19 | 2003-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-19 | 2006-10-19 | 2007-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-19 | 2010-10-19 | 2011-04-20 | $7700.00 | Window Closed / Lapsed |