PLL synthesizer having a reset circuit

Claim 2

A PLL frequency synthesizer for synchronizing an output frequency signal to a preset input frequency signal, said PLL frequency synthesizer comprising: a voltage controlled oscillator for generating the output frequency signal in response to a voltage signal; a comparison frequency divider for generating a comparison signal by dividing the output frequency signal from the voltage controlled oscillator; a phase comparator for receiving a reference signal having a predetermined frequency and the comparison signal and, in response to the reference signal and the comparison signal, for generating a first phase difference signal and a second phase difference signal, each of the first and second phase difference signals being representative of a respective phase difference between the reference signal and the comparison signal; a charge pump circuit for generating the voltage signal in response to the first and second phase difference signals, the charge pump having a first transistor being in an ON state in accordance with the first phase difference signal and a second transistor being in an ON state in accordance with the second phase difference signal; and a reset circuit for detecting the ON state of each of the first and second transistors of said charge pump circuit and for inhibiting the first and second phase difference signals generated by the phase comparator when the reset circuit detects that the first and second transistors of said charge pump circuit are both in the ON state, wherein said reset circuit includes: a first detection circuit including a first detection transistor for detecting that the first charge pump transistor is in the ON state; a second detection circuit including a second detection transistor for detecting that the second charge pump transistor is in the ON state; and a signal generating circuit connected to the first and second detection circuits for generating a reset signal to inhibit the first and second phase difference signals in response to the detection results of the first and second detection circuits.

Claim 3

A PLL frequency synthesizer according to claim 1, wherein said first processing circuit has a first CMOS circuit that includes the first detection transistor; and wherein said second processing circuit has a second CMOS circuit that includes the second detection transistor.

Claim 4

A PLL frequency synthesizer according to claim 1, wherein said first processing circuit includes a first inverter having the first detection transistor and a load resistor connected to the first detection transistor; and wherein said second processing circuit includes a second inverter having the second detection transistor and a load resistor connected to the second detection transistor.

Claim 5

A PLL frequency synthesizer according to claim 1, wherein the first detection transistor is a pMOS transistor and the second detection transistor is an nMOS transistor.

Claim 6

A PLL frequency synthesizer according to claim 2, wherein the first detection transistor is a pMOS transistor and the first CMOS circuit further includes a nMOS transistor, the pMOS transistor and the nMOS transistor being connected in series between a power supply V CC and a ground reference GND.

Claim 7

A PLL frequency synthesizer according to claim 3, wherein the first detection transistor is a pMOS transistor and the second detection transistor is an nMOS transistor, the first detection transistor and the load resistor are connected in series across a power supply and a ground reference, and the second detection transistor and the load resistor are also connected in series across the power supply and the ground reference.

Claim 8

A PLL frequency synthesizer comprising: a voltage controlled oscillator (VCO) generating an output frequency signal in response to a voltage signal; a comparison frequency divider receiving and frequency dividing the output frequency signal from the VCO to generate a comparison signal; a phase comparator receiving a reference signal having a predetermined frequency and the comparison signal, comparing a phase of the reference signal with a phase of the comparison signal, and generating a first phase difference signal and a second phase difference signal, wherein the first phase difference signal corresponds to the phase difference between the reference signal and the comparison signal when the phase of the reference signal leads the phase of the comparison signal and the second phase difference signal corresponds to the phase difference between the reference signal and the comparison signal when the phase of the comparison signal leads the phase of the reference signal, and the phase comparator further receiving a reset signal for inhibiting the first and second phase difference signals; a charge pump circuit, including first and second transistors connected in series between a power supply and ground, the first transistor receiving the first phase difference signal and the second transistor receiving the second phase difference signal, the charge pump generating the voltage signal at a node between the first and second transistors, wherein the first transistor is in an ON state in accordance with the first phase difference signal and the second transistor is in an ON state in accordance with the second phase difference signal; and a reset circuit detecting the ON state of each of the first and second charge pump transistors and inhibiting the first and second phase difference signals generated by the phase comparator when the first and second charge pump transistors are both in the ON state, wherein the reset circuit includes: a first detector having a pMOS transistor and an nMOS transistor connected in series between a power supply and ground, wherein the first phase difference signal is input to the gates of the pMOS and nMOS transistors and a first detector output signal is generated at a node between the pMOS transistor and the nMOS transistor; a second detector having a pMOS transistor and an nMOS transistor connected in series between the power supply and ground, wherein the second phase difference signal is input to the gates of the second detector pMOS and nMOS transistors and a second detector output signal is generated at a node between the second detector pMOS and nMOS transistors, and an inverter for receiving and inverting the second detector output signal; and a signal generator receiving the first detector output signal and the inverted second detector output signal and generating the reset signal therefrom.

Claim 9

A PLL frequency synthesizer comprising: a voltage controlled oscillator (VCO) generating an output frequency signal in response to a voltage signal; a comparison frequency divider receiving and frequency dividing the output frequency signal from the VCO to generate a comparison signal; a phase comparator receiving a reference signal having a predetermined frequency and the comparison signal, comparing a phase of the reference signal with a phase of the comparison signal, and generating a first phase difference signal and a second phase difference signal, wherein the first phase difference signal corresponds to the phase difference between the reference signal and the comparison signal when the phase of the reference signal leads the phase of the comparison signal and the second phase difference signal corresponds to the phase difference between the reference signal and the comparison signal when the phase of the comparison signal leads the phase of the reference signal, and the phase comparator further receiving a reset signal for inhibiting the first and second phase difference signals; a charge pump circuit, including first and second transistors connected in series between a power supply and ground, the first transistor receiving the first phase difference signal and the second transistor receiving the second phase difference signal, the charge pump generating the voltage signal at a node between the first and second transistors, wherein the first transistor is in an ON state in accordance with the first phase difference signal and the second transistor is in an ON state in accordance with the second phase difference signal; and a reset circuit detecting the ON state of each of the first and second charge pump transistors and inhibiting the first and second phase difference signals generated by the phase comparator when the first and second charge pump transistors are both in the ON state, wherein the reset circuit includes: a first detector having a pMOS transistor and an nMOS transistor connected in series between a power supply and ground, wherein the first phase difference signal is input to the gates of the pMOS and nMOS transistors and a first detector output signal is generated at a node between the pMOS transistor and the nMOS transistor; a second detector having a pMOS transistor and an nMOS transistor connected in series between the power supply and ground, wherein the second phase difference signal is input to the gates of the second detector pMOS and nMOS transistors and a second detector output signal is generated at a node between the second detector pMOS and nMOS transistors, and an inverter for receiving and inverting the second detector output signal; and a signal generator receiving the first detector output signal and the inverted second detector output signal and generating the reset signal therefrom.

Claim 10

A PLL frequency synthesizer comprising: a voltage controlled oscillator (VCO) for generating an output frequency signal in response to a voltage signal; a comparison frequency divider receiving and frequency dividing the output frequency signal from the VCO to generate a comparison signal; a phase comparator receiving a reference signal having a predetermined frequency and the comparison signal, comparing a phase of the reference signal with a phase of the comparison signal, and generating a first phase difference signal and a second phase difference signal, wherein the first phase difference signal corresponds to the phase difference between the reference signal and the comparison signal when the phase of the reference signal leads the phase of the comparison signal and the second phase difference signal corresponds to the phase difference between the reference signal and the comparison signal when the phase of the comparison signal leads the phase of the reference signal, and the phase comparator further receiving a reset signal for inhibiting the first and second phase difference signals; a charge pump circuit including first and second transistors connected in series between a power supply and ground, the first phase difference signal being input to the first transistor and the second phase difference signal being input to the second transistor, the charge pump circuit generating the voltage signal at a node between the first and second transistors, wherein the first transistor is in an ON state in accordance with the first phase difference signal and the second transistor is in an ON state in accordance with the second phase difference signal; and a reset circuit detecting the ON state of each of the first and second charge pump transistors and inhibiting the first and second phase difference signals generated by the phase comparator when the first and second charge pump transistors are both in the ON state, wherein the reset circuit includes: a first detector having a first transistor and a first load resistor connected in series between a power supply and ground, wherein the first phase difference signal is input to the first transistor and a first detector output signal is generated at a node between the first transistor and the first load resistor; a second detector having a second load resistor and a second transistor connected in series between the power supply and ground, wherein the second phase difference signal is input to the second transistor and a second detector output signal is generated at a node between the second load resistor and the second transistor, and an inverter for inverting the second detector output signal; and a signal generator receiving the first detector output signal and the inverted second detector output signal and generating the reset signal therefrom.

Claim 11

A PLL frequency synthesizer comprising: a voltage controlled oscillator (VCO) for generating an output frequency signal in response to a voltage signal; a comparison frequency divider receiving and frequency dividing the output frequency signal from the VCO to generate a comparison signal; a phase comparator receiving a reference signal having a predetermined frequency and the comparison signal, comparing a phase of the reference signal with a phase of the comparison signal, and generating a first phase difference signal and a second phase difference signal, wherein the first phase difference signal corresponds to the phase difference between the reference signal and the comparison signal when the phase of the reference signal leads the phase of the comparison signal and the second phase difference signal corresponds to the phase difference between the reference signal and the comparison signal when the phase of the comparison signal leads the phase of the reference signal, and the phase comparator further receiving a reset signal for inhibiting the first and second phase difference signals; a charge pump circuit including first and second transistors connected in series between a power supply and ground, the first phase difference signal being input to the first transistor and the second phase difference signal being input to the second transistor, the charge pump circuit generating the voltage signal at a node between the first and second transistors, wherein the first transistor is in an ON state in accordance with the first phase difference signal and the second transistor is in an ON state in accordance with the second phase difference signal; and a reset circuit detecting the ON state of each of the first and second charge pump transistors and inhibiting the first and second phase difference signals generated by the phase comparator when the first and second charge pump transistors are both in the ON state, wherein the reset circuit includes: a first detector having a first transistor and a first load resistor connected in series between a power supply and ground, wherein the first phase difference signal is input to the first transistor and a first detector output signal is generated at a node between the first transistor and the first load resistor; a second detector having a second load resistor and a second transistor connected in series between the power supply and ground, wherein the second phase difference signal is input to the second transistor and a second detector output signal is generated at a node between the second load resistor and the second transistor, and an inverter for inverting the second detector output signal; and a signal generator receiving the first detector output signal and the inverted second detector output signal and generating the reset signal therefrom.

Claim 12

The synthesizer of claim 8, wherein the reset circuit first transistor comprises a pMOS transistor and the reset circuit second transistor comprises an nMOS transistor.

Claim 13

The synthesizer of claim 8, wherein the reset circuit first transistor is an npn transistor and the reset circuit second transistor is a pnp transistor, and the charge pump first transistor is a pnp transistor and the charge pump second transistor is an npn transistor, the synthesizer further comprising: a third load resistor connected between the first phase difference signal input to the reset circuit first transistor and the power supply; and a fourth load resistor connected between the second phase difference signal input to the reset circuit second transistor and the ground.