DPSK demodulator which may be used in an interrogator of a remote intelligence communication system

Claim 2

A differential phase shift keyed demodulator which utilizes quadrature input signals that are supplied to and converted to quadrature digital outputs by analog to digital converters, comprising: a quadrature combiner responsive to the quadrature digital outputs for combining said outputs, wherein one of the quadrature digital outputs is delayed with respect to another undelayed output, and wherein the delayed and undelayed quadrature digital outputs are summed to produce combined output signals; a finite impulse response matched filter coupled to the quadrature combiner for filtering the combined output signals; and a time delay and multiplier circuit wherein a current filtered combined output signal is multiplied by a delayed filtered combined output signal to produce a demodulated output signal.

Claim 3

A demodulator as in claim 1 wherein the quadrature input signals are differentially phase shift keyed onto a single frequency sub-carrier.

Claim 4

A demodulator as in claim 1 wherein the FIR matched filter has a square time envelope.

Claim 5

A demodulator as in claim 2 wherein the FIR matched filter has a square time envelope and taps at the sub-carrier frequency.

Claim 6

A demodulator as in claim 2 wherein the multiplier circuit generates a two times the sub-carrier frequency signal.

Claim 7

A demodulator as in claim 5 further including a low pass filter responsive to the multiplier circuit for removing the two times the sub-carrier frequency signal.

Claim 8

A demodulator as in claim 1 further including a synchronization circuit of recovering a data clock from the demodulated output signal.

Claim 9

In a remote intelligent communication system including a programmable computer and a plurality of remote communication devices connected to the computer via an interrogator and a communications medium, said interrogator including a differential phase shift keyed demodulator which utilizes quadrature input signals that are supplied to and converted to quadrature digital outputs by analog to digital converters, a differential phase shift keyed demodulator comprising: a quadrature combiner responsive to the quadrature digital outputs for combining said outputs, wherein one of the quadrature digital outputs is delayed with respect to another undelayed output, and wherein the delayed and undelayed quadrature digital outputs are summed to produce combined output signals; a finite impulse response matched filter coupled to the quadrature combiner for filtering the combined output signals, and a time delay and multiplier circuit wherein a current filtered combined output signal is multiplied by a delayed filtered combined output signal to produce a demodulated output signal.

Claim 10

In a remote intelligent communication system including a programmable computer and a plurality of remote communication devices connected to the computer via an interrogator and a communications medium, said interrogator including a differential phase shift keyed demodulator which utilizes quadrature input signals that are supplied to and converted to quadrature digital outputs by analog to digital converters, a differential phase shift keyed demodulator comprising: a quadrature combiner responsive to the quadrature digital outputs for combining said outputs, wherein one of the quadrature digital outputs is delayed with respect to another undelayed output, and wherein the delayed and undelayed quadrature digital outputs are summed to produce combined output signals; a finite impulse response matched filter coupled to the quadrature combiner for filtering the combined output signals, and a time delay and multiplier circuit wherein a current filtered combined output signal is multiplied by a delayed filtered combined output signal to produce a demodulated output signal.

Claim 11

A system as in claim 8 wherein the remote communication devices are transducers which produce backscatter signals and the system further includes a downconverter for producing said quadrature input signals.

Claim 12

A system as in claim 9 wherein the quadrature input signals are differentially phase shift keyed onto a single frequency sub-carrier.

Claim 13

A system as in claim 9 wherein the quadrature input signals are filtered prior to being input to the analog to digital converters.

Claim 14

A system as in claim 8 wherein the FIR matched filter has a square time envelope.

Claim 15

A system as in claim 9 wherein the FIR matched filter has a square time envelope and has taps at the sub-carrier frequency.

Claim 16

A system as in claim 9 wherein the multiplier circuit generates a two times the sub-carrier frequency signal.

Claim 17

A system as in claim 14 further including a low pass filter responsive to the multiplier circuit for removing the two times the sub-carrier frequency signal.

Claim 18

A system as in claim 8 further including a synchronization circuit for recovering a data clock from the demodulated output signal.