US5895269A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods for preventing deleterious punch-through during local interconnect formation
Assignee: GlobalFoundries Inc
•
Filing: 1997-12-18
•
Granted: 1999-04-20
•
Expires: 2017-12-18
Abstract
Abstract During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. In order to prevent punch-through, the oxide spacers are removed prior to forming an overlying dielectric layer.
Inventors
- 👤 Fei Wang
- 👤 Minh Van Ngo
- 👤 Darin A. Chan
- 👤 David K. Foote
- 👤 William G. En
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:06
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10W20/0698
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
114 words
A method for avoiding over-etching into an underlying substrate during the formation of one or more local interconnects in a semiconductor wafer, the method comprising: forming a semiconductor device having a gate arrangement, a source region and a drain region, wherein the source region and the drain region are formed within a substrate, and the gate arrangement is formed on the substrate and includes a gate and at least one spacer that contacts the gate and the substrate, wherein the spacer is a dielectric; and removing at least a substantial portion of the spacer from the semiconductor device; and then forming a first dielectric layer over at least a portion of the semiconductor device.
Claim 2
Independent Claim
114 words
A method for avoiding over-etching into an underlying substrate during the formation of one or more local interconnects in a semiconductor wafer, the method comprising: forming a semiconductor device having a gate arrangement, a source region and a drain region, wherein the source region and the drain region are formed within a substrate, and the gate arrangement is formed on the substrate and includes a gate and at least one spacer that contacts the gate and the substrate, wherein the spacer is a dielectric; and removing at least a substantial portion of the spacer from the semiconductor device; and then forming a first dielectric layer over at least a portion of the semiconductor device.
Claim 3
Dependent Claim
51 words
The method as recited in claim 1, further comprising; selectively removing a portion of the first dielectric layer to expose a portion of the underlying semiconductor device through an opening; and creating a local interconnect by filling at least a portion of the opening with at least one electrically conductive material.
Claim 4
Dependent Claim
32 words
The method as recited in claim 1, wherein the gate arrangement includes a silicon dioxide layer on the substrate and the gate includes polysilicon and is formed on the silicon dioxide layer.
Claim 5
Dependent Claim
13 words
The method as recited in claim 3, wherein the spacer includes an oxide.
Claim 6
Dependent Claim
12 words
The method as recited in claim 3, wherein the spacer includes nitride.
Claim 7
Dependent Claim
29 words
The method as recited in claim 1, further comprising forming a second dielectric layer over the first dielectric layer, wherein the first and second dielectric layers are different materials.
Claim 8
Dependent Claim
52 words
The method as recited in claim 6, further comprising: selectively removing a portion of the first and second dielectric layers to expose a portion of the semiconductor device through an opening; and creating a local interconnect by filling at least a portion of the opening with at least one electrically conductive material.
Claim 9
Dependent Claim
33 words
The method as recited in claim 7, wherein selectively removing a portion of the first and second dielectric layers includes using an etching tool to etch through the first and second dielectric layers.
Claim 10
Dependent Claim
42 words
The method as recited in claim 8, wherein the etching through of the first and second dielectric layers includes anisotropically etching through the first dielectric layer with a first plasma and anisotropically etching through the second dielectric layer with a second plasma.
Claim 11
Dependent Claim
31 words
The method as recited in claim 1, wherein removing the spacer from the semiconductor device includes isotropically etching away at least a substantial portion of the spacer with an etching tool.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-19 | 2002-10-19 | 2003-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-19 | 2006-10-19 | 2007-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-19 | 2010-10-19 | 2011-04-20 | $7700.00 | Window Closed / Lapsed |