US5893155A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cache memory for efficient data logging
Assignee: Leland Stanford Junior University
•
Filing: 1996-12-03
•
Granted: 1999-04-06
•
Expires: 2016-12-03
Abstract
Abstract The present invention provides a digital computer memory cache organization for efficient data logging, log-based copy and rollback, high-performance I/O, network switching and multi-cache consistency maintenance. The cache organization implements efficient selective cache write-back, mapping and transferring of data. Write or store operations to cache lines tagged as logged are written through to a log block builder associated with the cache. Non-logged store operations are handled local to the cache, as in a writeback cache. The log block builder combines write operations into data blocks and transfers the data blocks to a log splitter. A log splitter demultiplexes the logged data into separate streams based on address.
Inventors
- 👤 David R. Cheriton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:39
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/1407; G06F11/30; G06F11/34; G06F11/3466; G06F11/3476; G06F12/0802; G06F12/0804; G06F12/0806; G06F12/0815; G06F12/0831; G06F11/348; G06F2201/00; G06F2201/885
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
68 words
A computer system comprising: a processor; a first-level cache coupled to receive data from the processor; a second-level cache coupled to said first-level cache through a first bus; and a log block builder, coupled to said first-level cache through a second bus, wherein when a write operation to a cache line marked as logged in the first-level cache occurs, the log block builder generates a log block output.
Claim 2
Dependent Claim
68 words
A computer system comprising: a processor; a first-level cache coupled to receive data from the processor; a second-level cache coupled to said first-level cache through a first bus; and a log block builder, coupled to said first-level cache through a second bus, wherein when a write operation to a cache line marked as logged in the first-level cache occurs, the log block builder generates a log block output.
Claim 3
Dependent Claim
37 words
The computing system of claim 1 further comprising: a log splitter coupled to receive said log block output, wherein said log splitter generates a revised log block output for a cache snooper component of said first-level cache.
Claim 4
Dependent Claim
53 words
The computing system of claim 1 wherein said first-level cache comprises: a cache controller coupled to said processor; and a cache directory coupled to said cache controller, said cache directory storing a status control word, wherein said cache controller generates a selected indication based on a status bit in said status control word.
Claim 5
Dependent Claim
62 words
The computing system of claim 1 wherein said log block builder comprises: an input port coupled to said first-level cache; a log block builder controller coupled to said input port and coupled to receive a selected indication from said first-level cache; and a log block register, coupled to said log block builder controller, said log block register forms said log block output.
Claim 6
Dependent Claim
18 words
The computing system of claim 1 wherein said log block output comprises an address of said write operation.
Claim 7
Dependent Claim
21 words
The computing system of claim 1 wherein said log block output comprises at least one data value of said write operation.
Claim 8
Dependent Claim
19 words
The computing system of claim 1 wherein said second-level cache receives said log block output via said first bus.
Claim 9
Dependent Claim
21 words
The computing system of claim 1 wherein said processor writes to said cache line marked as logged during said write operation.
Claim 10
Dependent Claim
22 words
The computing system of claim 1 wherein said processor, first level cache, and log block builder reside on a single integrated circuit.
Claim 11
Dependent Claim
23 words
The computing system of claim 1 wherein said processor, first-level cache, second-level cache, and log block builder reside on a single integrated circuit.
Claim 12
Dependent Claim
47 words
The computing system of claim 1 further comprising: a log splitter coupled to said first level cache through said first bus and to said second level cache memory through a third bus, wherein said log block output is passed from said second-level cache to said log splitter.
Claim 13
Dependent Claim
73 words
The computing system of claim 11 wherein said log splitter comprises: an address translation table; a log descriptor table; an address translation table control, coupled to access said address translation table, and receive an address of said log block output; and a log translation control module coupled to access said log description table and receive an output from said address translation table, wherein said log translation module generates a revised log address output.
Claim 14
Independent Claim
53 words
A method of using a cache comprising: issuing a transfer operation from a processor; accessing a cache line in a first-level cache associated with said transfer operation; and forming a log block comprising a transfer address and transfer data for said transfer operation when said cache line indicates it is to be logged.
Claim 15
Independent Claim
53 words
A method of using a cache comprising: issuing a transfer operation from a processor; accessing a cache line in a first-level cache associated with said transfer operation; and forming a log block comprising a transfer address and transfer data for said transfer operation when said cache line indicates it is to be logged.
Claim 16
Dependent Claim
21 words
The method of claim 13 further comprising: updating contents of a second-level cache with said transfer data in said log block.
Claim 17
Dependent Claim
27 words
The method of claim 13 further comprising: mapping the log block to a log buffer address; and forming a revised log block using said log buffer address.
Claim 18
Dependent Claim
16 words
The method of claim 15 further comprising: updating said first-level cache with said revised log block.
Claim 19
Independent Claim
95 words
A method for writing data to a memory unit within a computer having a processor and a cache memory comprising: receiving an address and a write instruction from said processor in a first cache memory; accessing and extracting datum resident in a cache directory of said first cache memory corresponding to said received address; incorporating said received address with said accessed datum into a log block; accessing a memory location in a second cache memory corresponding to said received address; and updating said memory location in said second cache memory according to said log block.
Claim 20
Independent Claim
95 words
A method for writing data to a memory unit within a computer having a processor and a cache memory comprising: receiving an address and a write instruction from said processor in a first cache memory; accessing and extracting datum resident in a cache directory of said first cache memory corresponding to said received address; incorporating said received address with said accessed datum into a log block; accessing a memory location in a second cache memory corresponding to said received address; and updating said memory location in said second cache memory according to said log block.
Claim 21
Independent Claim
111 words
An apparatus for writing data to a memory unit within a computer having a processor and a cache memory comprising: a first cache memory, receiving an address and a write instruction from said processor; first accessing means for accessing and extracting datum resident in said first cache memory corresponding to said received address from said processor; a log block builder to incorporate said received address with said accessed datum into a log block; a second cache memory, receiving said log block, wherein said second cache memory is updated using said log block; and a log splitter block, for receiving said log block, mapping said log block to a log buffer address.
Claim 22
Independent Claim
111 words
An apparatus for writing data to a memory unit within a computer having a processor and a cache memory comprising: a first cache memory, receiving an address and a write instruction from said processor; first accessing means for accessing and extracting datum resident in said first cache memory corresponding to said received address from said processor; a log block builder to incorporate said received address with said accessed datum into a log block; a second cache memory, receiving said log block, wherein said second cache memory is updated using said log block; and a log splitter block, for receiving said log block, mapping said log block to a log buffer address.
Claim 23
Dependent Claim
21 words
The apparatus of claim 18 wherein the first accessing means is a bus coupling said first cache memory and said processor.
Claim 24
Dependent Claim
22 words
The apparatus of claim 18 further comprising: a log block register coupled to said log block builder to store said log block.
References Cited (Backward Citations)
US4442487A
Cited
US4507751A
Cited
US4648031A
Cited
US4868744A
Cited
US5276851A
Cited
US5404489A
Cited
US5325504A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-05 | 2002-10-05 | 2003-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-05 | 2006-10-05 | 2007-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-05 | 2010-10-05 | 2011-04-06 | $7700.00 | Window Closed / Lapsed |