Parallel computer system using properties of messages to route them through an interconnect network and to select virtual channel circuits therewithin

Claim 2

A parallel processor system, comprising: a plurality of processor elements each including a processor; and a network which connects said plurality of processor elements for parallel transfer of plural messages therebetween; each processor element transmitting a message to said network, said message including property information of a predetermined kind and destination information of a predetermined kind, said property information of said predetermined kind having a value depending upon a type of said message and said destination information of said predetermined kind being related to a destination processor element; said network including a plurality of mutually connected switch circuits for transferring a plurality of messages each transmitted by one of said plurality of processor elements; each switch circuit including; a plurality of input terminals and a plurality of output terminals; and a route instruction circuit connected to said plurality of input terminals and said plurality of output terminals, responsive to a message supplied to one of plurality of input terminals for selecting one of said plurality of output terminals to which said message is to be transferred; wherein said route instruction circuit included in each of at least a first plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon the destination information of said predetermined kind included in said message; wherein said route instruction circuit included in each of at least a second plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon property information of said predetermined kind included in said message.

Claim 3

A parallel computer system according to claim 1, wherein each of said at least plural switch circuits can execute a plurality of modes of message transfer operations; wherein said property information of said predetermined kind included in a message transmitted by each processor element comprises transfer control information which indicates one of said plurality of modes of message transfer operations to be executed by switch circuits which will be involved in transmission of said message.

Claim 4

A parallel computer system according to claim 1, wherein said property information of said predetermined kind included in a message transmitted by each processor element comprises priority information which indicates a priority of said message.

Claim 5

A parallel computer system according to claim 1, wherein said property information included in a message transmitted by each processor element varies depending upon whether said message is transmitted by said each processor element on its own initiative or said message is transmitted to a destination processor element of said message as a response to another message transmitted to said each processor element from one of said plurality of processor elements different from said each processor element.

Claim 6

A parallel computer system according to claim 1, wherein said property information included in a message transmitted by each processor element has a value depending upon whether said message is an emergency message.

Claim 7

A parallel computer system according to claim 5, wherein said property information of said predetermined kind included in a message transmitted by each processor element has a value further depending upon whether said message is a message for synchronization of said processors or a message to be broadcasted to said plurality of processor elements.

Claim 8

A parallel computer system according to claim 1, wherein said route instruction circuit included in each of at least a third plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon said destination information of said predetermined kind included in said message and said property information of said predetermined kind included in said message.

Claim 9

A parallel processor system, comprising: a plurality of processor elements each including a processor; and a network which connects said plurality of processor elements for parallel transfer of plural messages therebetween; each processor element transmitting a message to said network, said message including property information of a predetermined kind and destination information of a predetermined kind, said property information of said predetermined kind having a value depending upon a type of message, said destination information of said predetermined kind being related to a destination processor element of said message; said network including a plurality of mutually connected switch circuits for transferring a plurality of messages each transmitted by one of said plurality of processor elements; each switch circuit including; a plurality of input terminals and a plurality of output terminals, a plurality of virtual channel circuits each provided in correspondence to and connected to one of said plurality of input terminals, and a route instruction circuit connected to said plurality of virtual channel circuits, responsive to a message supplied by one of said plurality of virtual channel circuits for selecting one of said plurality of output terminals to which said message is to be transferred; wherein each virtual channel circuit includes; a plurality of buffers each for holding at least part of a message; a first select circuit responsive to a message supplied to one of said plurality of input terminals to which said each virtual channel circuit is connected for selecting one of said plurality of buffers into which said message is to be held, and a second select circuit for selecting one of said plurality of buffers and for outputting a message held in said selected buffer, wherein said route instruction circuit included in each of at least a first plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon destination information of said predetermined kind included in said message; wherein said route instruction circuit included in each of at least a second plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals included in said each switch circuit to which a message supplied to said each switch circuit is to be transferred, depending upon property information of said predetermined kind included in said message.

Claim 10

A parallel processor system, comprising: a plurality of processor elements each including a processor; and a network which connects said plurality of processor elements for parallel transfer of plural messages therebetween; each processor element transmitting a message to said network, said message including property information of a predetermined kind and destination information of a predetermined kind, said property information of said predetermined kind having a value depending upon a type of message, said destination information of said predetermined kind being related to a destination processor element of said message; said network including a plurality of mutually connected switch circuits for transferring a plurality of messages each transmitted by one of said plurality of processor elements; each switch circuit including; a plurality of input terminals and a plurality of output terminals, a plurality of virtual channel circuits each provided in correspondence to and connected to one of said plurality of input terminals, and a route instruction circuit connected to said plurality of virtual channel circuits, responsive to a message supplied by one of said plurality of virtual channel circuits for selecting one of said plurality of output terminals to which said message is to be transferred; wherein each virtual channel circuit includes; a plurality of buffers each for holding at least part of a message; a first select circuit responsive to a message supplied to one of said plurality of input terminals to which said each virtual channel circuit is connected for selecting one of said plurality of buffers into which said message is to be held, and a second select circuit for selecting one of said plurality of buffers and for outputting a message held in said selected buffer, wherein said route instruction circuit included in each of at least a first plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon destination information of said predetermined kind included in said message; wherein said route instruction circuit included in each of at least a second plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals included in said each switch circuit to which a message supplied to said each switch circuit is to be transferred, depending upon property information of said predetermined kind included in said message.

Claim 11

A parallel computer system according to claim 8, wherein said property information of said predetermined kind included in a message transmitted by each processor element comprises priority information.

Claim 12

A parallel computer system according to claim 8, wherein said property information of said predetermined kind included in a message transmitted by each processor varies depending upon whether said message is transmitted by said each processor element on its own initiative or said message is transmitted to a destination processor element of said message as a response to another message transmitted to said each processor element from one of said plurality of processor elements different from said each processor element.

Claim 13

A parallel computer system according to claim 8, wherein said property information of said predetermined kind included in a message transmitted by each processor element has a value depending upon whether or not said message is an emergency message.

Claim 14

A parallel computer system according to claim 11, wherein said property information of said predetermined kind included in a message by each processor element has a value further depending upon whether said message is a message for synchronization of said plurality of processor elements or a message to be broadcasted to said plurality of processor elements.

Claim 15

A parallel computer system according to claim 8, wherein at least plural ones of said plurality of buffers of each virtual channel circuit are of mutually different sizes.

Claim 16

A parallel computer system according to claim 8, wherein each switch circuit has a control circuit for controlling transfer of a message supplied to said each switch circuit to another one of said plurality of switch circuits, according to one of a worm-hole method, a store-and-forward method and a virtual-cut-through method.

Claim 17

A parallel computer system according to claim 8, wherein each of said at least plural switch circuits can execute a plurality of modes of message transfer operations and said property information included in a message transmitted by each processor element comprises transfer control information which indicates one of said plurality of modes of message transfer operations to be executed by switch circuits which will be involved in transmission of said message.

Claim 18

A parallel computer system according to claim 8, wherein said route instruction circuit included in each of at least a third plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon said destination information of said predetermined kind included in said message and said property information of said predetermined kind included in said message.

Claim 19

A parallel processor system, comprising: a plurality of processor elements each including a processor; and a network which connects said plurality of processor elements for parallel transfer of plural messages therebetween; said network including a plurality of mutually connected switch circuits for transferring a plurality of messages each transmitted by one of said plurality of processor elements; each switch circuit including; a plurality of input terminals and a plurality of output terminals, a plurality of virtual channel circuits each provided in correspondence to and connected to one of said plurality of input terminals; wherein each virtual channel circuit comprises a plurality of buffers each for holding at least part of a message; wherein a message held in each of said plurality of buffers within said each virtual channel is one of a message type predetermined for said each buffer among a plurality of types of messages transferred by the network to one of said plurality of input terminals connected to said each virtual channel; wherein at least plural ones of said plurality of buffers of each virtual channel circuit are of mutually different sizes; wherein a size of each buffer is one adopted to a size of a message of a predetermined type which said each buffer can hold.

Claim 20

A parallel processor system, comprising: a plurality of processor elements each including a processor; and a network which connects said plurality of processor elements for parallel transfer of plural messages therebetween; said network including a plurality of mutually connected switch circuits for transferring a plurality of messages each transmitted by one of said plurality of processor elements; each switch circuit including; a plurality of input terminals and a plurality of output terminals, a plurality of virtual channel circuits each provided in correspondence to and connected to one of said plurality of input terminals; wherein each virtual channel circuit comprises a plurality of buffers each for holding at least part of a message; wherein a message held in each of said plurality of buffers within said each virtual channel is one of a message type predetermined for said each buffer among a plurality of types of messages transferred by the network to one of said plurality of input terminals connected to said each virtual channel; wherein at least plural ones of said plurality of buffers of each virtual channel circuit are of mutually different sizes; wherein a size of each buffer is one adopted to a size of a message of a predetermined type which said each buffer can hold.

Claim 21

A parallel processor system, comprising: a plurality of processor elements each including a processor; and a network which connects said plurality of processor elements for parallel transfer of plural data therebetween; each processor element transmitting to said network, data to be transmitted to a destination processor element together with property information of a predetermined kind and destination information of a predetermined kind, said property information of said predetermined kind having a value depending upon a type of said data to be transmitted, and said destination information of said predetermined kind being related to said destination processor element; said network including a plurality of mutually connected switch circuits for transferring a plurality of data to be transmitted each transmitted by one of said plurality of processor elements; each switch circuit including; a plurality of input terminals and a plurality of output terminals; and a route instruction circuit connected to said plurality of input terminals and said plurality of output terminals, responsive to data to be transmitted supplied to one of plurality of input terminals for selecting one of said plurality of output terminals to which said data to be transmitted is to be transferred; wherein said route instruction circuit included in each of at least a first plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon destination information of said predetermined kind transmitted with said data to be transmitted; wherein said route instruction circuit included in each of at least a second plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon property information of said predetermined kind transmitted with said data to be transmitted.

Claim 22

A parallel processor system, comprising: a plurality of processor elements each including a processor; and a network which connects said plurality of processor elements for parallel transfer of plural data therebetween; each processor element transmitting to said network, data to be transmitted to a destination processor element together with property information of a predetermined kind and destination information of a predetermined kind, said property information of said predetermined kind having a value depending upon a type of said data to be transmitted, and said destination information of said predetermined kind being related to said destination processor element; said network including a plurality of mutually connected switch circuits for transferring a plurality of data to be transmitted each transmitted by one of said plurality of processor elements; each switch circuit including; a plurality of input terminals and a plurality of output terminals; and a route instruction circuit connected to said plurality of input terminals and said plurality of output terminals, responsive to data to be transmitted supplied to one of plurality of input terminals for selecting one of said plurality of output terminals to which said data to be transmitted is to be transferred; wherein said route instruction circuit included in each of at least a first plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon destination information of said predetermined kind transmitted with said data to be transmitted; wherein said route instruction circuit included in each of at least a second plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon property information of said predetermined kind transmitted with said data to be transmitted.

Claim 23

A parallel computer system according to claim 18, wherein each of said at least plural switch circuits can execute a plurality of modes of data transfer operations; wherein said property information of said predetermined kind transmitted with said data to be transmitted as transmitted by each processor element comprises transfer control information which indicates one of said plurality of modes of data transfer operations to be executed by switch circuits which will be involved in transmission of said data to be transmitted.

Claim 24

A parallel computer system according to claim 18, wherein said property information of said predetermined kind transmitted with data to be transmitted as transmitted by each processor element comprises priority information which indicates a priority of said data to be transmitted.

Claim 25

A parallel processor system, comprising: a plurality of processor elements each including a processor; and a network which connects said plurality of processor elements for parallel transfer of plural data therebetween; each processor element transmitting to said network, data to be transmitted to a destination processor element, together with property information of a predetermined kind and destination information of a predetermined kind, said property information of said predetermined kind having a value depending upon a type of said data to be transmitted, said destination information of said predetermined kind being related to said destination processor element; said network including a plurality of mutually connected switch circuits for transferring a plurality of data to be transmitted each transmitted by one of said plurality of processor elements; each switch circuit including; a plurality of input terminals and a plurality of output terminals, a plurality of virtual channel circuits each provided in correspondence to and connected to one of said plurality of input terminals, and a route instruction circuit connected to said plurality of virtual channel circuits, responsive to data to be transmitted as supplied by one of said plurality of virtual channel circuits for selecting one of said plurality of output terminals to which said data to be transmitted is to be transferred; wherein each virtual channel circuit includes; a plurality of buffers each for holding at least part of data to be transmitted; a first select circuit responsive to data to be transmitted as supplied to one of said plurality of input terminals to which said each virtual channel circuits is connected for selecting one of said plurality of buffers into which said data to be transmitted is to be held, and a second select circuit for selecting one of said plurality of buffers and for outputting data to be transmitted held in said selected buffer, wherein said route instruction circuit included in each of at least a first plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon destination information of said predetermined kind transmitted with said data to be transmitted; wherein said route instruction circuit included in each of at least a second plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon property information of said predetermined kind transmitted with said data to be transmitted.

Claim 26

A parallel processor system, comprising: a plurality of processor elements each including a processor; and a network which connects said plurality of processor elements for parallel transfer of plural data therebetween; each processor element transmitting to said network, data to be transmitted to a destination processor element, together with property information of a predetermined kind and destination information of a predetermined kind, said property information of said predetermined kind having a value depending upon a type of said data to be transmitted, said destination information of said predetermined kind being related to said destination processor element; said network including a plurality of mutually connected switch circuits for transferring a plurality of data to be transmitted each transmitted by one of said plurality of processor elements; each switch circuit including; a plurality of input terminals and a plurality of output terminals, a plurality of virtual channel circuits each provided in correspondence to and connected to one of said plurality of input terminals, and a route instruction circuit connected to said plurality of virtual channel circuits, responsive to data to be transmitted as supplied by one of said plurality of virtual channel circuits for selecting one of said plurality of output terminals to which said data to be transmitted is to be transferred; wherein each virtual channel circuit includes; a plurality of buffers each for holding at least part of data to be transmitted; a first select circuit responsive to data to be transmitted as supplied to one of said plurality of input terminals to which said each virtual channel circuits is connected for selecting one of said plurality of buffers into which said data to be transmitted is to be held, and a second select circuit for selecting one of said plurality of buffers and for outputting data to be transmitted held in said selected buffer, wherein said route instruction circuit included in each of at least a first plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon destination information of said predetermined kind transmitted with said data to be transmitted; wherein said route instruction circuit included in each of at least a second plurality of switch circuits within said plurality of mutually connected switch circuits executes said selecting of one of said plurality of output terminals, depending upon property information of said predetermined kind transmitted with said data to be transmitted.

Claim 27

A parallel computer system according to claim 21, wherein each of said at least plural switch circuits can execute a plurality of modes of data transfer operations, wherein said property information transmitted with data to be transmitted as transmitted by each processor element comprises transfer control information which indicates one of said plurality of modes of data transfer operations to be executed by switch circuits which will be involved in transmission of said data to be transmitted.

Claim 28

A parallel computer system according to claim 21, wherein said property information of said predetermined kind transmitted with data to be transmitted as transmitted by each processor element comprises priority information.