US5892256A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory and a method of manufacturing the same
Assignee: Sony Corp
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Filing: 1997-02-21
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Granted: 1999-04-06
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Expires: 2017-02-21
Abstract
Abstract A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and semiconductor regions formed on the surface of the insulating layer. The semiconductor memory is characterized in that the MIS transistors are formed, respectively, on the surfaces of the semiconductor regions and separated from each other and from the semiconductor substrate by an insulating layer, and the capacitors are formed, respectively, under the corresponding MIS transistors. The insulating layer separating the MIS transistors from each other and from the semiconductor substrate reduces current leakage between the storage cells and reduces capacitance across bit lines formed on the side of the MIS transistors and the semiconductor substrate. The method of manufacturing the semiconductor memory includes a lapping process for lapping the surface of a wafer in forming the semiconductor regions in recesses formed by the insulating layer. The lapping process uses an alkaline liquid as a lapping liquid and employs a lapping disk provided with a hard lapping pad to finish the surfaces of the semiconductor regions flush with the surface of the insulating layer by lapping.
Inventors
- 👤 Takeshi Matsushita
- 👤 Muneharu Shimanoe
- 👤 Hiroshi Sato
- 👤 Akira Nieda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:41
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/33; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/37; H10B12/373
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
154 words
A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, said capacitor having first and second electrodes separated by a dielectric film comprising: a substrate; a layer of polycrystalline material adjacent said substrate; an insulating layer formed on said layer of polycrystalline material; semiconductor regions, each formed as a single crystal on the surface of said insulating layer; wherein the semiconductor regions are surrounded by and flush with the insulating layer with said insulating layer extending below said semiconductor regions, the MIS transistors are formed, respectively, in said single crystal semiconductor regions; the capacitors are formed, respectively, under the corresponding MIS transistors and the dielectric film is embedded within said layer of polycrystalline material; the polycrystalline material serves as the first electrode of the capacitors; and the second electrode of each of the capacitors is connected electrically to the MIS transistors through contact holes formed in the insulating layer.
Claim 2
Dependent Claim
154 words
A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, said capacitor having first and second electrodes separated by a dielectric film comprising: a substrate; a layer of polycrystalline material adjacent said substrate; an insulating layer formed on said layer of polycrystalline material; semiconductor regions, each formed as a single crystal on the surface of said insulating layer; wherein the semiconductor regions are surrounded by and flush with the insulating layer with said insulating layer extending below said semiconductor regions, the MIS transistors are formed, respectively, in said single crystal semiconductor regions; the capacitors are formed, respectively, under the corresponding MIS transistors and the dielectric film is embedded within said layer of polycrystalline material; the polycrystalline material serves as the first electrode of the capacitors; and the second electrode of each of the capacitors is connected electrically to the MIS transistors through contact holes formed in the insulating layer.
Claim 3
Dependent Claim
35 words
The semiconductor memory according to claim 1, wherein said capacitors are connected electrically to said MIS transistors through contact holes through said insulating layer, with said substrate serving as a common electrode of said capacitors.
Claim 4
Dependent Claim
145 words
A semiconductor memory device comprising: a substrate; a layer of polycrystalline material formed on said substrate; an insulating layer formed on said layer of polycrystalline material; semiconductor regions, each formed as a single crystal on a first surface of said insulating layer have a top surface that forms a substantially planar surface with a second surface of the insulating layer; wherein the semiconductor regions are surrounded by the insulating layer with said insulating layer extending below said semiconductor regions, source-drain regions of transistors formed in said single crystal semiconductor regions; capacitors formed under corresponding ones of the transistors and dielectric films for the capacitors embedded within the layer of polycrystalline material; the polycrystalline material forming a first electrode of the capacitors; and the second electrode of each of the capacitors being connected electrically to the MIS transistors through contact holes formed in the insulating layer.
Claim 5
Dependent Claim
145 words
A semiconductor memory device comprising: a substrate; a layer of polycrystalline material formed on said substrate; an insulating layer formed on said layer of polycrystalline material; semiconductor regions, each formed as a single crystal on a first surface of said insulating layer have a top surface that forms a substantially planar surface with a second surface of the insulating layer; wherein the semiconductor regions are surrounded by the insulating layer with said insulating layer extending below said semiconductor regions, source-drain regions of transistors formed in said single crystal semiconductor regions; capacitors formed under corresponding ones of the transistors and dielectric films for the capacitors embedded within the layer of polycrystalline material; the polycrystalline material forming a first electrode of the capacitors; and the second electrode of each of the capacitors being connected electrically to the MIS transistors through contact holes formed in the insulating layer.
Claim 6
Dependent Claim
34 words
The semiconductor memory according to claim 3, wherein said capacitors are connected electrically to said transistors through contact holes in said insulating layer, with said substrate serving as a common electrode of said capacitors.
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