US5890190A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frame buffer for storing graphics and video data
Assignee: Intel Corp
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Filing: 1995-06-07
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Granted: 1999-03-30
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Expires: 2015-06-07
Abstract
Abstract A single frame buffer system is provided for displaying pixels of differing types according to standard pixel information types. Memory receives the pixel information wherein the pixel associated with each item of pixel information is further associated with a control signal for indicating the pixel type of the associated pixel. Devices for interpreting each type of pixel information to provide pixel display information are provided. Based upon the pixel type control signal, the associated pixel information is interpreted by the correct interpretation device to provide the pixel display information. The different pixel types may be graphics pixels and video pixels. In this case the output of either graphics processing circuitry or the output of video processing circuitry is selected for display according to the control signal. This single frame buffer system is effective to provide one-to-one mapping between the received pixel information and displayed pixels. The pixel type control signal may also include a signal representative of the number of consecutive pixels of one of the two pixel types.
Inventors
- 👤 Sergei Rutman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:55
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G2340/00; G09G2340/12; G09G2340/125; G09G2360/00; G09G2360/12; G09G5/02; G09G5/399
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
235 words
A single frame buffer architecture system in a system for processing for display digital graphics signals and digital video signals, the single frame buffer architecture system comprising: (a) a graphics controller for receiving combined digital video signals and digital graphics signals over a single bus, the digital video signals comprising a plurality of video pixels and the digital graphics signals comprising a plurality of graphics pixels, wherein each digital video pixels and each digital graphics pixel includes a data type bit indicating the digital video pixel or digital graphics pixel as comprising one of a video pixel or graphics pixel; (b) a VRAM for receiving said combined digital video signals and digital graphics signals from said graphics controller and for storing said combined digital video signals and digital graphics signals; and (c) means for receiving the data type bits whereby the processing system is instructed by each data type bit to process the digital video or digital graphics pixel associated with said data type bit as a video pixel or a graphics pixel, respectively; wherein said means for receiving comprises a decoding means, and further comprising a multiplexing means coupled to said decoding means, said multiplexing means receiving the digital video signals and digital graphics signals, said decoding means instructing said multiplexing means to process individual ones of the digital video signals or digital graphics signals as a video pixel or a graphic pixels, respectively.
Claim 2
Dependent Claim
235 words
A single frame buffer architecture system in a system for processing for display digital graphics signals and digital video signals, the single frame buffer architecture system comprising: (a) a graphics controller for receiving combined digital video signals and digital graphics signals over a single bus, the digital video signals comprising a plurality of video pixels and the digital graphics signals comprising a plurality of graphics pixels, wherein each digital video pixels and each digital graphics pixel includes a data type bit indicating the digital video pixel or digital graphics pixel as comprising one of a video pixel or graphics pixel; (b) a VRAM for receiving said combined digital video signals and digital graphics signals from said graphics controller and for storing said combined digital video signals and digital graphics signals; and (c) means for receiving the data type bits whereby the processing system is instructed by each data type bit to process the digital video or digital graphics pixel associated with said data type bit as a video pixel or a graphics pixel, respectively; wherein said means for receiving comprises a decoding means, and further comprising a multiplexing means coupled to said decoding means, said multiplexing means receiving the digital video signals and digital graphics signals, said decoding means instructing said multiplexing means to process individual ones of the digital video signals or digital graphics signals as a video pixel or a graphic pixels, respectively.
Claim 3
Dependent Claim
30 words
The system of claim 1, further comprising means for converting the digital video signals and digital graphics signals to analog video signals and analog graphics signals, respectively, suitable for display.
Claim 4
Dependent Claim
25 words
The system of claim 2, wherein the digital video and digital graphics signals are stored according to the positions in which they will be displayed.
Claim 5
Dependent Claim
39 words
The system of claim 2, wherein the means for converting comprises the means for receiving the identifiers, whereby the means for converting selectively converts digital video signals to analog video signals and digital graphics signals to analog graphics signals.
Claim 6
Dependent Claim
43 words
The system of claim 1, further comprising a digital video signals path and a digital graphics signals path, wherein the combined video signals and digital graphics signals are coupled to each of the digital video signals path and the digital graphics signals path.
Claim 7
Independent Claim
209 words
A method for processing for display digital graphics signals and digital video signals in a single frame buffer architecture system, comprising the steps of: (a) receiving with a graphic controller combined digital video and digital graphics signals over a single bus, the digital video signals comprising a plurality of video pixels and the digital graphics signals comprising a plurality of graphics pixels, wherein each digital video pixel and each digital graphics pixel includes a data type bit indicating the digital video pixel or digital graphics pixel as comprising one of a video pixel or graphics pixel; (b) receiving said combined digital video signals and digital graphics signals from said graphics controller and storing with a VRAM said combined digital video signals and digital graphics signals; and (c) receiving and interpreting the data type bits whereby the processing system is instructed by each data type bit to process the digital video or digital graphics pixel associated with said data type bit as a video pixel or a graphics pixel, respectively; wherein said receiving step further comprising decoding and multiplexing the digital video signals and the digital graphics signals to process individual ones of the digital video signals or digital graphics signal as a video pixel or a graphics pixel, respectively.
Claim 8
Independent Claim
209 words
A method for processing for display digital graphics signals and digital video signals in a single frame buffer architecture system, comprising the steps of: (a) receiving with a graphic controller combined digital video and digital graphics signals over a single bus, the digital video signals comprising a plurality of video pixels and the digital graphics signals comprising a plurality of graphics pixels, wherein each digital video pixel and each digital graphics pixel includes a data type bit indicating the digital video pixel or digital graphics pixel as comprising one of a video pixel or graphics pixel; (b) receiving said combined digital video signals and digital graphics signals from said graphics controller and storing with a VRAM said combined digital video signals and digital graphics signals; and (c) receiving and interpreting the data type bits whereby the processing system is instructed by each data type bit to process the digital video or digital graphics pixel associated with said data type bit as a video pixel or a graphics pixel, respectively; wherein said receiving step further comprising decoding and multiplexing the digital video signals and the digital graphics signals to process individual ones of the digital video signals or digital graphics signal as a video pixel or a graphics pixel, respectively.
Claim 9
Dependent Claim
38 words
The process of claim 6, further comprising the steps of converting the digital video signals and digital graphics signals to analog video signals and analog graphics signals, respectively, and displaying the analog video signals and analog graphics signals.
Claim 10
Dependent Claim
29 words
The process claim 7, wherein the step of storing comprises storing the digital video signals and digital graphics signals according to the positions in which they will be displayed.
Claim 11
Dependent Claim
27 words
The process of claim 7, wherein the step of converting selectively converts digital video signals to analog video signals and digital graphics signals to analog graphics signals.
Claim 12
Dependent Claim
34 words
The process of claim 6, further comprising the step of transmitting the combined digital video signals and digital graphics signals along a separate digital video signals path and a separate digital graphics signals path.
Claim 13
Dependent Claim
53 words
The process of claim 6, wherein step (b) includes the step of multiplexing the digital video signals and digital graphics signals whereby individual one of the digital video signals and digital graphics signals are multiplexed for processing as a video pixel or a graphics pixel, respectively, as instructed by the data type bits.
Claim 14
Dependent Claim
206 words
A single frame buffer architecture in a system for processing for display digital graphics and digital video signals, comprising: a graphic controller for receiving combined digital video signals and digital graphics signals over a single bus, the digital video signals comprising a plurality of video pixels and the digital graphics signals comprising a plurality of graphics pixels, wherein each digital video pixel and each digital graphics pixel includes a data type bit indicating the digital video pixel or digital graphics pixel as comprising one of a video pixel or graphic pixel; a VRAM for receiving said combined digital video signals and digital graphics signals from said graphics controller and for storing said combined digital video signals and digital graphics signals; and a multiplexer for receiving the data type bits whereby the multiplexer is instructed by each data type bit to process the digital video or digital graphics pixel associated with said data type bit as a video pixel or a graphics pixels, respectively; a decoder further coupled to said multiplexer for first decoding the data type bits, whereby the multiplexer is instructed by the decoder to process individual ones of the digital video signals or digital graphics signals as video pixels or a graphics pixels, respectively.
Claim 15
Dependent Claim
206 words
A single frame buffer architecture in a system for processing for display digital graphics and digital video signals, comprising: a graphic controller for receiving combined digital video signals and digital graphics signals over a single bus, the digital video signals comprising a plurality of video pixels and the digital graphics signals comprising a plurality of graphics pixels, wherein each digital video pixel and each digital graphics pixel includes a data type bit indicating the digital video pixel or digital graphics pixel as comprising one of a video pixel or graphic pixel; a VRAM for receiving said combined digital video signals and digital graphics signals from said graphics controller and for storing said combined digital video signals and digital graphics signals; and a multiplexer for receiving the data type bits whereby the multiplexer is instructed by each data type bit to process the digital video or digital graphics pixel associated with said data type bit as a video pixel or a graphics pixels, respectively; a decoder further coupled to said multiplexer for first decoding the data type bits, whereby the multiplexer is instructed by the decoder to process individual ones of the digital video signals or digital graphics signals as video pixels or a graphics pixels, respectively.
Claim 16
Dependent Claim
34 words
The architecture of claim 12, further comprising a digital to analog converter for converting the digital video signals and digital graphics signals to analog video signals and analog graphics signals, respectively, suitable for display.
Claim 17
Dependent Claim
29 words
The architecture of claim 13, wherein the digital video signals and digital graphics signals are stored in the memory according to the positions in which they will be displayed.
Claim 18
Dependent Claim
40 words
The architecture of claim 13, wherein the digital to analog converter comprises the multiplexer, whereby the digital to analog converter is operable to selectively convert digital video signals to analog video signals and digital graphics signals to analog graphics signals.
Claim 19
Dependent Claim
44 words
The architecture of claim 12, further comprising a digital video signals path and a digital graphics signals path, wherein the combined digital video signals and digital graphics signals are coupled to each of the digital video signals path and the digital graphics signals path.
References Cited (Backward Citations)
GB2073997A
Cited
US4868765A
Cited
US4991014A
Cited
US5347624A
Cited
US4907086A
Cited
US5025249A
Cited
US5216413A
Cited
US4947257A
Cited
EP0384257A2
Cited
US5097257A
Cited
US5257348A
Cited
US5274753A
Cited
EP0484970A2
Cited
US5245322A
Cited
US5230041A
Cited
WO1993021623A1
Cited
US5345554A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-29 | 2002-09-28 | 2003-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-29 | 2006-09-28 | 2007-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-29 | 2010-09-28 | 2011-03-30 | $7700.00 | Window Closed / Lapsed |