US5889727A
Expired / Lapsed
US
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Circuit for reducing the transmission delay of the redundancy evaluation for synchronous DRAM
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-05-11
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Granted: 1999-03-30
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Expires: 2018-05-11
Abstract
Abstract The present invention discloses a circuit that reduces the transmission delay of the redundancy evaluation for SDRAM. After an input address is decoded as an external address, the external address is routed to a global factor generator to generate global factors accompanied with an address strobe pulse. The external address is also routed to a redundancy check circuit for starting the redundancy evaluation. Therefore, the redundancy evaluation can be performed as soon as the external address comes. While the external address comes, a column burst pulse and a system clock are directed to the internal counter of the global factor generator for counting continuously. The current count value is treated as an internal address and then routed to the redundancy check circuit to output the ready redundancy evaluation. After the redundancy evaluation and a column synchronous pulse generated by the global column factor generator come to a column redundancy latch, a signal that indicates whether a normal or a redundant memory cell is accessed is sent to a local column factor generator. Finally, a normal or a redundancy bit-line selector is generated to enable a read/write operation. Therefore, the transmission delay that is caused by awaiting the generation of the redundancy evaluation can be significantly reduced.
Inventors
- 👤 Peter K. Y. Hsu
- 👤 Jonathan Y. P. Chou
- 👤 Tsun-Chu Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:35
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
112 words
A circuit for reducing a transmission delay of a redundancy evaluation in a synchronous dynamic random access memory (SDRAM), wherein said circuit comprises: Global factor generating means responsive to an external address for generating a global factor and an internal address; redundancy evaluating means responsive to said internal address for generating a redundancy evaluation, said redundancy evaluation being output when said external address arrives; redundancy status buffering means responsive to said redundancy evaluation for generating a path evaluation that indicates whether a redundancy memory cell is accessed; and local factor generating means responsive to said global factor and said path evaluation for generating a local factor that enables a memory accessing operation.
Claim 2
Dependent Claim
112 words
A circuit for reducing a transmission delay of a redundancy evaluation in a synchronous dynamic random access memory (SDRAM), wherein said circuit comprises: Global factor generating means responsive to an external address for generating a global factor and an internal address; redundancy evaluating means responsive to said internal address for generating a redundancy evaluation, said redundancy evaluation being output when said external address arrives; redundancy status buffering means responsive to said redundancy evaluation for generating a path evaluation that indicates whether a redundancy memory cell is accessed; and local factor generating means responsive to said global factor and said path evaluation for generating a local factor that enables a memory accessing operation.
Claim 3
Dependent Claim
116 words
The circuit according to claim 1, wherein said redundancy evaluating means comprises: a plurality of fuse sets for receiving said internal address and a fuse precharge signal to generate fused information that indicates a logic-state stored in said fuse set according to said internal address; a plurality of MOS (Metal-Oxide-Semiconductor) transistors, each said MOS transistor having a gate, a source, and a drain, all said gates of said MOS transistors being used to receive said fused information, all said sources of said MOS transistors being coupled together, and all said drains of said MOS transistors being coupled together; and redundancy loading means coupled with all said drains of said MOS transistors for generating said redundancy evaluation.
Claim 4
Dependent Claim
35 words
The circuit according to claim 2, wherein each said fuse set comprises a fuse that is fusedly connected or blown to indicate whether a normal memory cell or a redundant memory cell is accessed, respectively.
Claim 5
Dependent Claim
34 words
The circuit according to claim 1, wherein said global factor generating means comprises an internal address counter for generating said internal address that enables said redundancy evaluating means to output said redundancy check evaluation.
Claim 6
Dependent Claim
31 words
The circuit according to claim 1, wherein said redundancy status buffering means couples with said redundancy status buffering means to enable said redundancy status buffering means to output said path evaluation.
Claim 7
Dependent Claim
19 words
The circuit according to claim 1, wherein said memory accessing operation is a memory-read operation or a memory-write operation.
Claim 8
Dependent Claim
20 words
The circuit according to claim 1, wherein said global factor is a global column factor or a global row factor.
Claim 9
Dependent Claim
20 words
The circuit according to claim 1, wherein said local factor is a local column factor or a local row factor.
Claim 10
Dependent Claim
166 words
A circuit for reducing a transmission delay of a redundancy evaluation in a synchronous dynamic random access memory (SDRAM), wherein said circuit comprises: address buffering means for decoding an input address to generate an external address; global factor generating means responsive to said external address for generating a global factor and an internal address, said global factor generating means comprises an internal address counter for generating said internal address; redundancy evaluating means responsive to said external address and said internal address for generating a redundancy evaluation; redundancy status buffering means responsive to said redundancy evaluation and said internal address for generating a path evaluation that indicates whether a redundancy memory cell is accessed, said redundancy status buffering means couples with said redundancy evaluation means to enable said redundancy status buffering means to output said path evaluation when said internal address arrives; and local factor generating means responsive to said global factor and said path evaluation for generating a local factor that enables a memory accessing operation.
Claim 11
Dependent Claim
166 words
A circuit for reducing a transmission delay of a redundancy evaluation in a synchronous dynamic random access memory (SDRAM), wherein said circuit comprises: address buffering means for decoding an input address to generate an external address; global factor generating means responsive to said external address for generating a global factor and an internal address, said global factor generating means comprises an internal address counter for generating said internal address; redundancy evaluating means responsive to said external address and said internal address for generating a redundancy evaluation; redundancy status buffering means responsive to said redundancy evaluation and said internal address for generating a path evaluation that indicates whether a redundancy memory cell is accessed, said redundancy status buffering means couples with said redundancy evaluation means to enable said redundancy status buffering means to output said path evaluation when said internal address arrives; and local factor generating means responsive to said global factor and said path evaluation for generating a local factor that enables a memory accessing operation.
Claim 12
Dependent Claim
116 words
The circuit according to claim 9, wherein said redundancy evaluating means comprises: a plurality of fuse sets for receiving said internal address and a fuse precharge signal to generate fused information that indicates a logic-state according to said internal address; a plurality of MOS (Metal-Oxide-Semiconductor) transistors, each said MOS transistor having a gate, a source, and a drain, all said gates of said MOS transistors being used to receive said fused information according to said internal address, all said sources of said MOS transistors being coupled together, all and said drains of said MOS transistors being coupled together; and redundancy loading means coupled with all said drains of said MOS transistors for generating said redundancy evaluation.
Claim 13
Dependent Claim
35 words
The circuit according to claim 10, wherein each said fuse set comprises a fuse that is fusedly connected or blown to indicate whether a normal memory cell or a redundant memory cell is accessed, respectively.
Claim 14
Dependent Claim
19 words
The circuit according to claim 9, wherein said memory accessing operation is a memory-read operation or a memory-write operation.
Claim 15
Dependent Claim
20 words
The circuit according to claim 9, wherein said global factor is a global column factor or a global row factor.
Claim 16
Dependent Claim
20 words
The circuit according to claim 9, wherein said local factor is a local column factor or a local row factor.
Claim 17
Independent Claim
94 words
A method for reducing a transmission delay of a redundancy evaluation in a synchronous dynamic random access memory (SDRAM), said method comprising the steps of: inputting an external address; generating a redundancy evaluation by using said external address; generating a global factor by using said external address; generating an internal address by using a system clock outputting said redundancy evaluation when said internal address arrives; generating a path evaluation by using said redundancy evaluation; and generating a local factor that enables a memory accessing operation by using said global factor and said path evaluation.
Claim 18
Independent Claim
94 words
A method for reducing a transmission delay of a redundancy evaluation in a synchronous dynamic random access memory (SDRAM), said method comprising the steps of: inputting an external address; generating a redundancy evaluation by using said external address; generating a global factor by using said external address; generating an internal address by using a system clock outputting said redundancy evaluation when said internal address arrives; generating a path evaluation by using said redundancy evaluation; and generating a local factor that enables a memory accessing operation by using said global factor and said path evaluation.
Claim 19
Dependent Claim
18 words
The method according to claim 15, wherein said path evaluation indicates whether a redundancy memory cell is accessed.
Claim 20
Dependent Claim
19 words
The method according to claim 15, wherein said memory accessing operation is a memory-read operation or a memory-write operation.
Claim 21
Dependent Claim
20 words
The circuit according to claim 15, wherein said global factor is a global column factor or a global row factor.
Claim 22
Dependent Claim
20 words
The circuit according to claim 15, wherein said local factor is a local column factor or a local row factor.
Claim 23
Dependent Claim
27 words
The method according to claim 15, wherein said redundancy evaluation is performed by detecting a fuse set indicated by said external address is fusedly connected or blown.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-29 | 2002-09-28 | 2003-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-29 | 2006-09-28 | 2007-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-29 | 2010-09-28 | 2011-03-30 | $7700.00 | Window Closed / Lapsed |