US5887187A — Single chip network adapter apparatus

Claim 1

Independent Claim 170 words

A single chip network adapter apparatus, comprising: a host interface circuit adapted for connection directly to a host system bus, the host interface circuit being operative to send information to and receive information from the host system bus; random access memory (RAM) for storing information in a network protocol format and in a host computer format, said RAM coupled to the host interface circuit; a microprocessor coupled to the random access memory for formatting information received from the host system bus to a network protocol format, and for converting information received in a network protocol format to said host computer format; and a network interface circuit coupled to the random access memory and adapted for connection directly to a network, the network interface circuit being operative to send information formatted by the processor to the network and to receive information to be converted by the processor from the network; the host interface circuit, the random access memory, the processor, and the network interface circuit being disposed on a single chip.

Claim 2

Dependent Claim 170 words

A single chip network adapter apparatus, comprising: a host interface circuit adapted for connection directly to a host system bus, the host interface circuit being operative to send information to and receive information from the host system bus; random access memory (RAM) for storing information in a network protocol format and in a host computer format, said RAM coupled to the host interface circuit; a microprocessor coupled to the random access memory for formatting information received from the host system bus to a network protocol format, and for converting information received in a network protocol format to said host computer format; and a network interface circuit coupled to the random access memory and adapted for connection directly to a network, the network interface circuit being operative to send information formatted by the processor to the network and to receive information to be converted by the processor from the network; the host interface circuit, the random access memory, the processor, and the network interface circuit being disposed on a single chip.

Claim 3

Dependent Claim 50 words

The single chip network apparatus according to claim 1, further comprising: a direct memory access (DMA) circuit coupled to the host interface circuit for controlling the transfer of information to and from an external memory coupled to the host system bus; the DMA circuit being disposed on said single chip.

Claim 4

Dependent Claim 26 words

The single chip network apparatus according to claim 2, wherein the host interface circuit is adapted for connection directly to a parallel cell interface (PCI) bus.

Claim 5

Dependent Claim 30 words

The single chip network apparatus according to claim 3, wherein the network interface circuit comprises asynchronous transfer mode (ATM) segmentation and assembly circuity for use with an ATM network protocol.

Claim 6

Dependent Claim 20 words

The single chip network apparatus according to claim 4, wherein the network interface circuit further comprises ATM transmission convergence circuits.

Claim 7

Dependent Claim 28 words

The single chip network apparatus according to claim 3, wherein the network interface circuit further comprises synchronous optical network/synchronous digital hierarchy (SONET/SDH) framers for interfacing to a network.

Claim 8

Dependent Claim 27 words

The single chip network apparatus according to claim 3, wherein the network interface circuit further comprises a physical layer circuit adapted for connection directly to the network.

Claim 9

Dependent Claim 213 words

A host system connected to a network, comprising in combination: a host processor; a host system bus coupled to the host processor for transferring digital data to and from the host processor; host random access memory coupled to the host system bus for storing digital data; and a network adapter apparatus constructed on a single semiconductor substrate having a first port coupled to the host system bus and having a second port coupled to a network, the apparatus including a host bus interface circuit coupled to the first port, a direct memory access controller circuit coupled to the host bus interface circuit for transferring digital data to and from the host random access memory, a microprocessing unit coupled to the host bus interface circuit, random access memory RAM for storing information in a network protocol format and in a host computer format, said RAM coupled to the microprocessing unit, a network interface circuit coupled to the second port and coupled to the microprocessing unit, the microprocessing unit being operative to format digital data received from the host system bus into packets of data consistent with a network protocol and to format digital data received via the second port into packets of data consistent with a network protocol suitable for the host system bus.

Claim 10

Dependent Claim 213 words

A host system connected to a network, comprising in combination: a host processor; a host system bus coupled to the host processor for transferring digital data to and from the host processor; host random access memory coupled to the host system bus for storing digital data; and a network adapter apparatus constructed on a single semiconductor substrate having a first port coupled to the host system bus and having a second port coupled to a network, the apparatus including a host bus interface circuit coupled to the first port, a direct memory access controller circuit coupled to the host bus interface circuit for transferring digital data to and from the host random access memory, a microprocessing unit coupled to the host bus interface circuit, random access memory RAM for storing information in a network protocol format and in a host computer format, said RAM coupled to the microprocessing unit, a network interface circuit coupled to the second port and coupled to the microprocessing unit, the microprocessing unit being operative to format digital data received from the host system bus into packets of data consistent with a network protocol and to format digital data received via the second port into packets of data consistent with a network protocol suitable for the host system bus.

Claim 11

Dependent Claim 19 words

The host system according to claim 8, wherein the processing unit comprises a reduced instruction set computer (RISC)-based processor.

Claim 12

Dependent Claim 16 words

The host system according to claim 8, wherein the processing unit comprises a logic controller circuit.

Claim 13

Dependent Claim 17 words

The host system according to claim 8, wherein the network is an asynchronous transfer mode (ATM) network.

Claim 14

Dependent Claim 14 words

The host system according to claim 8, wherein the network is an Ethernet network.

Claim 15

Dependent Claim 18 words

The host system according to claim 8, wherein the network is a fiber distributed data interface (FDDI) network.

Claim 16

Dependent Claim 19 words

The host system according to claim 8, wherein the host system bus is a parallel cell interface (PCI) bus.

Claim 17

Dependent Claim 20 words

The host system according to claim 8, wherein the host system bus is an extended industry standard architecture (EISA) bus.

Claim 18

Dependent Claim 15 words

The host system according to claim 8, wherein the host system bus is an S-bus.

Claim 19

Dependent Claim 26 words

The single chip network adapter apparatus according to claim 2, wherein the network interface circuit includes a physical-layer medium dependent (PMDI) circuit on said single chip.

Claim 20

Dependent Claim 29 words

The single chip network adapter apparatus according to claim 17, wherein the network interface circuit includes an asynchronous transfer mode transmission convergence (ATM TC) circuit on said single chip.

Claim 21

Dependent Claim 30 words

The single chip network adapter apparatus according to claim 18, wherein the network interface circuit includes an asynchronous transfer mode segmentation and reassembly (ATM SAR) circuit on said single chip.

Claim 22

Dependent Claim 140 words

A single chip network adapter apparatus on a single semiconductor substrate, comprising: a PMD circuit for interconnection to an ATM network; a TC/Framer circuit coupled to the PMD circuit; an ATM SAR circuit coupled to the PMD circuit; microprocessor means coupled to the ATM SAR circuit for converting ATM packets of data to an internal data format; an internal data bus coupled to said microprocessor means for converting ATM packets of data; a direct memory access controller coupled to the internal data bus; and a PCI bus interface circuit coupled to the direct memory access controller, and being adapted for connection to an external data bus, whereby data in the internal data format can be transferred to and from an external bus; each of the components of the single chip network adapter apparatus being disposed on a single semiconductor substrate.

Claim 23

Dependent Claim 140 words

A single chip network adapter apparatus on a single semiconductor substrate, comprising: a PMD circuit for interconnection to an ATM network; a TC/Framer circuit coupled to the PMD circuit; an ATM SAR circuit coupled to the PMD circuit; microprocessor means coupled to the ATM SAR circuit for converting ATM packets of data to an internal data format; an internal data bus coupled to said microprocessor means for converting ATM packets of data; a direct memory access controller coupled to the internal data bus; and a PCI bus interface circuit coupled to the direct memory access controller, and being adapted for connection to an external data bus, whereby data in the internal data format can be transferred to and from an external bus; each of the components of the single chip network adapter apparatus being disposed on a single semiconductor substrate.

Claim 24

Dependent Claim 47 words

The single chip network adapter apparatus according to claim 20, further comprising random access memory on said single substrate for temporarily storing packets of digital information in an ATM network protocol format, the random access memory being coupled to said means for converting ATM packets of data.

Claim 25

Dependent Claim 187 words

A single chip network adapter apparatus on a single semiconductor substrate, comprising; a physical layer circuit for interfacing to an ATM network; an ATM cell interface circuit coupled to the physical layer circuit; a virtual channel RAM (VCR) coupled to the ATM cell interface; a DMA-VCR bus coupled to the virtual channel RAM; a direct memory access controller coupled to the DMA-VCR bus; a random access memory for storing packets of data in an ATM network protocol format, the random access memory being coupled to the direct memory access controller; an internal data bus coupled to the direct memory access controller; an ATM microprocessing unit (APU) for converting data in an ATM network protocol format to an internal data format, said APU being coupled to the internal data bus; a host data bus coupled to the direct memory access controller; a shared host RAM memory coupled to the host data bus for storing data in the internal data format; and a host processor coupled to the host data bus; each of the components of the single chip network adapter apparatus being disposed on a single semiconductor substrate.

Claim 26

Dependent Claim 187 words

A single chip network adapter apparatus on a single semiconductor substrate, comprising; a physical layer circuit for interfacing to an ATM network; an ATM cell interface circuit coupled to the physical layer circuit; a virtual channel RAM (VCR) coupled to the ATM cell interface; a DMA-VCR bus coupled to the virtual channel RAM; a direct memory access controller coupled to the DMA-VCR bus; a random access memory for storing packets of data in an ATM network protocol format, the random access memory being coupled to the direct memory access controller; an internal data bus coupled to the direct memory access controller; an ATM microprocessing unit (APU) for converting data in an ATM network protocol format to an internal data format, said APU being coupled to the internal data bus; a host data bus coupled to the direct memory access controller; a shared host RAM memory coupled to the host data bus for storing data in the internal data format; and a host processor coupled to the host data bus; each of the components of the single chip network adapter apparatus being disposed on a single semiconductor substrate.

Claim 27

Dependent Claim 32 words

The single chip network adapter apparatus according to claim 22, further comprising on said single semiconductor substrate: a pacing rate unit coupled to the internal data bus and coupled to the APU.

Claim 28

Dependent Claim 33 words

The single chip network adapter apparatus according to claim 23, further comprising on said single semiconductor substrate: an instruction RAM coupled to the APU for storing instructions to be executed by the APU.

Claim 29

Dependent Claim 146 words

A single chip network adapter apparatus on a single semiconductor substrate, comprising: means for interconnecting to an ATM network; a random access memory for storing ATM cells; means for processing and segmentation and reassembly, said means being coupled to the means for interconnecting to an ATM network; a microprocessor for converting ATM cells to an internal data format, said microprocessor being coupled to the means for storing ATM cells; an internal data bus coupled to said means for converting ATM packets of data; a direct memory access means coupled to the internal data bus for controlling transfers of information to and from said random access memory; and external bus interface means for connection to an external data bus, said means being coupled to the direct memory access means; each of the components of the single chip network adapter apparatus being disposed on a single semiconductor substrate.

Claim 30

Dependent Claim 146 words

A single chip network adapter apparatus on a single semiconductor substrate, comprising: means for interconnecting to an ATM network; a random access memory for storing ATM cells; means for processing and segmentation and reassembly, said means being coupled to the means for interconnecting to an ATM network; a microprocessor for converting ATM cells to an internal data format, said microprocessor being coupled to the means for storing ATM cells; an internal data bus coupled to said means for converting ATM packets of data; a direct memory access means coupled to the internal data bus for controlling transfers of information to and from said random access memory; and external bus interface means for connection to an external data bus, said means being coupled to the direct memory access means; each of the components of the single chip network adapter apparatus being disposed on a single semiconductor substrate.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-03-22	2002-09-21	2003-03-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-03-22	2006-09-21	2007-03-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-03-22	2010-09-21	2011-03-23	$7700.00	Window Closed / Lapsed

Single chip network adapter apparatus

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