Semiconductor memory device with increased coupling ratio

Claim 2

A semiconductor memory device comprising: a semiconductor substrate; a tunneling film formed on said semiconductor substrate; first and second gates formed on said tunneling film; a dielectric layer formed between said first and second gates; and first and second impurity regions formed in said semiconductor substrate adjacent said tunneling film, one of said first gate and said second gate having a projecting portion, wherein said first gate is a floating gate, and said floating gate includes, a first floating gate formed on said tunneling film, a second floating gate projecting from one side of said first floating gate, a third floating gate projecting from another side of said first floating gate, a fourth floating gate connected to said second floating gate and being parallel to said first floating gate, and a fifth floating gate connected to said third floating gate and being parallel to said first floating gate.

Claim 3

A semiconductor memory device as claimed in claim 1, wherein the projection portion includes at least one bent portion.

Claim 4

A semiconductor memory device as claimed in claim 1, wherein said second gate is a control gate.

Claim 5

A semiconductor memory device as claimed in claim 3, wherein said control gate includes: a first control gate formed on said dielectric layer, a second control gate projecting from said first control gate, and a third control gate connected to said second control gate and being parallel to said first control gate.

Claim 6

A semiconductor memory device as claimed in claim 3, wherein said control gate includes: a first control gate formed on said dielectric layer, a second control gate projecting from one side of said first control gate, a third control gate projecting from another side of said first control gate, a fourth control gate connected to said second control gate and being parallel to said first control gate, and a fifth control gate connected to said third control and being parallel to said first control gate.

Claim 7

A semiconductor memory device as claimed in claim 1, wherein said tunneling film is formed of an oxide film.

Claim 8

A semiconductor memory device as claimed in claim 1, wherein said dielectric layer is formed of a high temperature and low pressure dielectric.

Claim 9

A semiconductor memory device as claimed in claim 1, wherein said first gate overlaps said first and second impurity regions at edges of said first gate.

Claim 10

A semiconductor memory device as claimed in claim 1, wherein said first and second impurity regions are formed of high concentration n-type ions.

Claim 11

A semiconductor memory device as claimed in claim 1, wherein one of said first and second gates has an I-shape.

Claim 12

A semiconductor memory device as claimed in claim 1, wherein said first gate has a jar shape.

Claim 13

A semiconductor memory device as claimed in claim 1, wherein ends of said first gate, said dielectric layer, and said second gate are aligned with respect to said first impurity region.

Claim 14

A semiconductor memory device as claimed in claim 12, wherein other ends of said first gate, said dielectric layer, and said second gate are aligned with respect to said second impurity region.

Claim 15

A semiconductor memory device comprising: a semiconductor substrate; a tunneling insulating film formed on said semiconductor substrate; a first gate formed on said tunneling insulating film; a second gate formed on said tunneling insulating film; a dielectric layer formed between said first and second gates; and first and second impurity regions formed in said semiconductor substrate adjacent said first gate, wherein said first gate includes, a first floating gate formed on said tunneling insulating film, second and third floating gates formed on and extending from ends of said first floating gate, a fourth floating gate formed on said second floating gate such that one side thereof is connected to said second floating gate and another side thereof extends toward said third floating gate, and a fifth floating gate formed on said third floating gate such that one side thereof is connected to said third floating gate and another side thereof extends toward second floating gate.

Claim 16

A semiconductor memory device comprising: a semiconductor substrate; a tunneling insulating film formed on said semiconductor substrate; a first gate formed on said tunneling insulating film; a second gate formed on said tunneling insulating film; a dielectric layer formed between said first and second gates; and first and second impurity regions formed in said semiconductor substrate adjacent said first gate, wherein said first gate includes, a first floating gate formed on said tunneling insulating film, second and third floating gates formed on and extending from ends of said first floating gate, a fourth floating gate formed on said second floating gate such that one side thereof is connected to said second floating gate and another side thereof extends toward said third floating gate, and a fifth floating gate formed on said third floating gate such that one side thereof is connected to said third floating gate and another side thereof extends toward second floating gate.

Claim 17

A semiconductor memory device as claimed in claim 14, wherein said fourth floating gate and said fifth floating gate are substantially coplanar, said second gate separating said fourth and fifth floating gates.

Claim 18

A semiconductor memory device as claimed in claim 14, wherein said first gate is a floating gate and said second gate is a control gate.

Claim 19

A semiconductor memory device as claimed in claim 14, wherein said first gate is a control gate and said second gate is a floating gate.

Claim 20

A semiconductor memory device comprising: a semiconductor substrate; a tunneling film formed on said semiconductor substrate; first and second gates formed on said tunneling film; a dielectric layer formed between said first and second gates; and first and second impurity regions formed in said semiconductor substrate adjacent said tunneling film, one of said first gate and said second gate having a projecting portion, wherein said second gate is a control gate, and said control gate includes, a first control gate formed on said dielectric layer, a second control gate projecting from one side of said first control gate, a third control gate projecting from another side of said first control gate, a fourth control gate connected to said second control gate and being parallel to said first control gate, and a fifth control gate connected to said third control and being parallel to said first control gate.

Claim 21

A semiconductor memory device comprising: a semiconductor substrate; a tunneling film formed on said semiconductor substrate; first and second gates formed on said tunneling film; a dielectric layer formed between said first and second gates; and first and second impurity regions formed in said semiconductor substrate adjacent said tunneling film, one of said first gate and said second gate having a projecting portion, wherein said second gate is a control gate, and said control gate includes, a first control gate formed on said dielectric layer, a second control gate projecting from one side of said first control gate, a third control gate projecting from another side of said first control gate, a fourth control gate connected to said second control gate and being parallel to said first control gate, and a fifth control gate connected to said third control and being parallel to said first control gate.

Claim 22

A semiconductor memory device comprising: a semiconductor substrate; a tunneling film formed on said semiconductor substrate; first and second gates formed on said tunneling film; a dielectric layer formed between said first and second gates; and first and second impurity regions formed in said semiconductor substrate adjacent said tunneling film, one of said first gate and said second gate having a projecting portion, wherein said second gate includes, first and second gate members formed on portions of said first gate, third and fourth gate members projecting perpendicularly from sides of said first and second gate members, and a fifth gate member connected to said third and fourth gate members and being parallel to said first gate.

Claim 23

A semiconductor memory device comprising: a semiconductor substrate; a tunneling film formed on said semiconductor substrate; first and second gates formed on said tunneling film; a dielectric layer formed between said first and second gates; and first and second impurity regions formed in said semiconductor substrate adjacent said tunneling film, one of said first gate and said second gate having a projecting portion, wherein said second gate includes, first and second gate members formed on portions of said first gate, third and fourth gate members projecting perpendicularly from sides of said first and second gate members, and a fifth gate member connected to said third and fourth gate members and being parallel to said first gate.

Claim 24

A semiconductor memory device comprising: a semiconductor substrate; a tunneling film formed on said semiconductor substrate; first and second gates formed on said tunneling film; a dielectric layer formed between said first and second gates; and first and second impurity regions formed in said semiconductor substrate adjacent said tunneling film, one of said first gate and said second gate having a projecting portion, wherein said first gate includes, a first gate member formed on said tunneling film, second and third gate members projecting perpendicularly from sides of said first gate member, and fourth and fifth gate members respectively connected to said second and third gate members and being parallel to said first gate member.

Claim 25

A semiconductor memory device comprising: a semiconductor substrate; a tunneling film formed on said semiconductor substrate; first and second gates formed on said tunneling film; a dielectric layer formed between said first and second gates; and first and second impurity regions formed in said semiconductor substrate adjacent said tunneling film, one of said first gate and said second gate having a projecting portion, wherein said first gate includes, a first gate member formed on said tunneling film, second and third gate members projecting perpendicularly from sides of said first gate member, and fourth and fifth gate members respectively connected to said second and third gate members and being parallel to said first gate member.