US5882962A
Expired / Lapsed
US
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Method of fabricating MOS transistor having a P+ -polysilicon gate
Assignee: Vanguard International Semiconductor Corp
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Filing: 1996-07-29
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Granted: 1999-03-16
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Expires: 2016-07-29
Abstract
Abstract A method of forming a MOS transistor having a p + -polysilicon gate includes doping an amorphous silicon layer with phosphorus, thereby forming a n - amorphous silicon layer atop of a gate oxide. The n - amorphous silicon layer is then doped with boron to convert the n - amorphous silicon layer into a p + -amorphous silicon layer. The p + -amorphous silicon layer is then thermally treated to convert the p + -amorphous silicon layer into a p + -polysilicon layer. The p + -polysilicon layer is then patterned into a gate for a MOS transistor. The phosphorus ions in the p + -polysilicon help to fix the boron ions in the polysilicon gate, thereby reducing the diffusion of the boron ions and penetration of boron into the gate oxide.
Inventors
- 👤 Kuo-Shu Tseng
- 👤 Chi-Hua Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:15
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10D64/01312; H10D64/663; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/014; H10D84/0147; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
210 words
A method of manufacturing a PMOS transistor having a p + -polysilicon gate, the method comprising: forming a silicon dioxide layer on a semiconductor substrate; forming a first doped silicon layer on said silicon dioxide layer, said first doped silicon layer comprising n-amorphous silicon; forming a undoped silicon layer on said first doped silicon layer, said undoped silicon layer comprising undoped amorphous silicon; forming second doped silicon layer on said silicon dioxide layer, said second doped silicon layer comprising n-amorphous silicon; forming a tungsten silicide layer on said second doped silicon layer; doping said first doped, said undoped and said second doped silicon layers with a p-type dopant, wherein said first doped silicon, said undoped and said second doped silicon layers comprise p + -amorphous silicon; thermally treating said first doped, said undoped and said second doped silicon layers to convert said amorphous silicon of said first doped, said undoped and said second doped silicon layers to polysilicon; patterning and etching said metal silicide layer, said first doped, said undoped and said second doped silicon layers and said silicon dioxide layer to form a gate structure; and forming source and drain regions in said substrate using ion implantation of p-type dopants, said metal silicide layer serving as an implant mask.
Claim 2
Independent Claim
210 words
A method of manufacturing a PMOS transistor having a p + -polysilicon gate, the method comprising: forming a silicon dioxide layer on a semiconductor substrate; forming a first doped silicon layer on said silicon dioxide layer, said first doped silicon layer comprising n-amorphous silicon; forming a undoped silicon layer on said first doped silicon layer, said undoped silicon layer comprising undoped amorphous silicon; forming second doped silicon layer on said silicon dioxide layer, said second doped silicon layer comprising n-amorphous silicon; forming a tungsten silicide layer on said second doped silicon layer; doping said first doped, said undoped and said second doped silicon layers with a p-type dopant, wherein said first doped silicon, said undoped and said second doped silicon layers comprise p + -amorphous silicon; thermally treating said first doped, said undoped and said second doped silicon layers to convert said amorphous silicon of said first doped, said undoped and said second doped silicon layers to polysilicon; patterning and etching said metal silicide layer, said first doped, said undoped and said second doped silicon layers and said silicon dioxide layer to form a gate structure; and forming source and drain regions in said substrate using ion implantation of p-type dopants, said metal silicide layer serving as an implant mask.
Claim 3
Dependent Claim
28 words
The method of claim 1, wherein said first doped silicon layer is doped by diffusion with phosphorus using a SiH 4 and PH 3 mixture as a source.
Claim 4
Dependent Claim
26 words
The method of claim 1, wherein said first and second doped silicon layers have a dopant concentration of about 10 17 -10 18 atoms/cm 3 .
Claim 5
Dependent Claim
28 words
The method of claim 1, wherein said second doped silicon layer is doped by diffusion with phosphorus using a SiH 4 and PH 3 mixture as a source.
Claim 6
Dependent Claim
22 words
The method of claim 1, wherein the dosage of said implantation to form p-silicon layer is higher than 6E15 atoms/cm 2 .
Claim 7
Dependent Claim
29 words
The method of claim 1, wherein said thermally treating said first doped, said undoped and said second doped silicon layers is performed using a temperature of about 700-900° C.
References Cited (Backward Citations)
US4637836A
Cited
US5464789A
Cited
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