US5879568A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for producing multilayer printed circuit board for wire bonding
Assignee: Hitachi Ltd
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Filing: 1997-06-06
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Granted: 1999-03-09
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Expires: 2017-06-06
Abstract
Abstract A multilayer printed circuit board small in interlayer thickness, capable of fine wiring, minimized in IVH and BVH diameters, high in strength and also excellent in wire bonding workability can be produced by a process comprising the steps of coating a thermosetting resin varnish compounded with electrically insulating whiskers on a roughened side of a copper foil, semi-curing the resin by heating to form a thermosetting resin layer, integrally laminating it on an interlayer board in which plated through-holes and conductor circudits have been formed, and roughening the cured thermosetting resin layer on the via hole wall surfaces with a roughening agent.
Inventors
- 👤 Naoyuki Urasaki
- 👤 Kouichi Tsuyama
- 👤 Kazuhito Kobayashi
- 👤 Norio Okano
- 👤 Hiroshi Shimizu
- 👤 Nobuyuki Ogawa
- 👤 Akishi Nakaso
- 👤 Toyoki Ito
- 👤 Daisuke Fujimoto
- 👤 Kazuhisa Otsuka
- 👤 Shigeharu Arike
- 👤 Yoshiyuki Tsuru
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:40
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4644; H05K3/4652; H05K3/4655; H05K3/40; H05K3/42; H05K3/429; H05K1/00; H05K1/02; H05K1/0296; H05K1/0298; H05K1/11; H05K1/115; H05K3/0011; H05K3/0017; H05K3/0026; H05K3/0032; H05K3/0035; H05K3/10; H05K3/103; H05K2201/00; H05K2201/02; H05K2201/0203; H05K2201/0206; H05K2201/0209; H05K2201/0242; H05K2201/0248; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0355; H05K2201/0358; H05K2203/00; H05K2203/05; H05K2203/0548; H05K2203/0554; H05K3/0094; H05K3/02; H05K3/022; H05K3/025; H05K3/4673; H05K3/4676; H10; H10W; H10W72/00; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
243 words
A process for producing a multilayer printed circuit board comprising the following steps (a)-(h) which are carried out in this order: (a) compounding electrically insulating ceramic whiskers in a thermosetting resin varnish, dispersing the whiskers in the varnish uniformly by stirring, coating the resulting mixture on a roughened side of a copper foil, semi-curing the resin by heating to form a thermosetting resin layer, placing this layer on an interlayer circuit board in which plated through-holes and conductor circuits have been formed, and hot pressing them to form an integral laminate; (b) forming an etching resist on said copper foil, and etching the copper foil portions exposed from the etching resist into the shape of holes for forming interstitial via holes; (c) removing the etching resist; (d) applying laser beams to the cured thermosetting resin layer exposed from the fine holes of the copper foil etched into the shape of holes for forming interstitial via holes to remove said resin layer to an extent that the circuit conductors of the interlayer board is to be exposed, thereby forming via holes; (e) roughening said cured thermosetting resin layer on the walls of said via holes by using a roughening agent; (f) conducting plating to electrically connect the circuit conductors of the interlayer board and the copper foil; (g) forming an etching resist on said copper foil and etching away the copper foil portions exposed from said etching resist; and (h) removing the etching resist.
Claim 2
Dependent Claim
243 words
A process for producing a multilayer printed circuit board comprising the following steps (a)-(h) which are carried out in this order: (a) compounding electrically insulating ceramic whiskers in a thermosetting resin varnish, dispersing the whiskers in the varnish uniformly by stirring, coating the resulting mixture on a roughened side of a copper foil, semi-curing the resin by heating to form a thermosetting resin layer, placing this layer on an interlayer circuit board in which plated through-holes and conductor circuits have been formed, and hot pressing them to form an integral laminate; (b) forming an etching resist on said copper foil, and etching the copper foil portions exposed from the etching resist into the shape of holes for forming interstitial via holes; (c) removing the etching resist; (d) applying laser beams to the cured thermosetting resin layer exposed from the fine holes of the copper foil etched into the shape of holes for forming interstitial via holes to remove said resin layer to an extent that the circuit conductors of the interlayer board is to be exposed, thereby forming via holes; (e) roughening said cured thermosetting resin layer on the walls of said via holes by using a roughening agent; (f) conducting plating to electrically connect the circuit conductors of the interlayer board and the copper foil; (g) forming an etching resist on said copper foil and etching away the copper foil portions exposed from said etching resist; and (h) removing the etching resist.
Claim 3
Dependent Claim
146 words
A process according to claim 1, wherein the following steps (a1) and (a2) are used in place of the step (a): (a1) compounding electrically insulating ceramic whiskers in a thermosetting resin varnish, dispersing the whiskers in the varnish uniformly by stirring, coating the resulting mixture on a roughened side of a copper layer of a composite metal foil comprising a circuit-forming copper layer having an appropriate roughness for bonding with the resin and a carrier layer having a sufficient strength to stand handling as a metal layer as a whole, said two layers being easily separable from each other, semi-curing the resin by heating to form a thermosetting resin layer, placing this resin layer on an interlayer circuit board in which the plated through-holes and conductor circuits have been formed, and hot pressing them to form an integral laminate; and (a2) removing the carrier layer alone.
Claim 4
Dependent Claim
169 words
A process according to claim 1, wherein the following steps (a3) to (a5) are used in place of the step (a): (a3) compounding electrically insulating ceramic whiskers in a thermosetting resin varnish, dispersing the whiskers in the varnish uniformly by stirring, coating the resulting mixture on a roughened side of a first copper layer of a composite metal foil comprising a circuit-forming 1-9 μm thick first copper foil having an appropriate roughness for bonding with the resin, a 10-150 μm thick second copper layer having a sufficient strength to stand handling as a metal layer as a whole and a 0.04-1.5 μm thick nickel-phosphorus alloy layer disposed between said first and second copper layers, semi-curing the resin by heating to form a thermosetting resin layer, placing this resin layer on an interlayer circuit board in which the plated through-holes and conductor circuits have been formed, and hot pressing them to form an integral laminate; (a4) removing the second copper layer alone; and (a5) removing the nickel-phosphorus alloy layer alone.
Claim 5
Dependent Claim
39 words
A process according to any one of claims 1-3, wherein the steps of (a) to (h), (a1) to (h), or (a3) to (h) are repeated a necessary number of times to form two or more layers of via holes.
Claim 6
Dependent Claim
33 words
A process according to any one of claims 1-3, wherein the thermosetting resin flow is 500 μm or greater, and the thickness of the semi-cured thermosetting resin layer is 25 to 100 μm.
Claim 7
Dependent Claim
28 words
A process according to any one of claims 1-3, wherein the amount of the electrically insulating whiskers compounded in the thermoseting resin is 5 to 50% by volume.
Claim 8
Dependent Claim
30 words
A process according to claim 4, wherein the thermosetting resin flow is 500 μm or greater, and the thickness of the semi-cured thermosetting resin layer is 25 to 100 μm.
Claim 9
Dependent Claim
25 words
A process according to claim 4, wherein the amount of the electrically insulating whiskers compounded in the thermosetting resin is 5 to 50% by volume.
References Cited (Backward Citations)
US4943346A
Cited
JPH04338695A
Cited
US5263243A
Cited
JPH06260760A
Cited
US5651899A
Cited
US5567329A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-08 | 2002-09-07 | 2003-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-08 | 2006-09-07 | 2007-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-08 | 2010-09-07 | 2011-03-09 | $7700.00 | Window Closed / Lapsed |